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參數(shù)資料
| 型號： | MC9328MXLVP20 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 微處理器 |
| 英文描述： | i.MX Integrated Portable System Processor |
| 中文描述： | i.MX處理器集成的便攜式系統(tǒng) |
| 文件頁數(shù)： | 2/96頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | MC9328MXLVP20 |
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MC9328MX1 Advance Information, Rev. 4
2
Freescale Semiconductor
Introduction
Figure 1. MC9328MX1 Functional Block Diagram
1.1 Conventions
This document uses the following conventions:
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one
is a voltage that corresponds to Boolean true (1) state.
Logic level zero
is a voltage that corresponds to Boolean false (0) state.
To
set
a bit or bits means to establish logic level one.
To
clear
a bit or bits means to establish logic level zero.
A
signal
is an electronic construct whose state conveys or changes in state convey information.
A
pin
is an external physical connection. The same pin can be used to connect a number of signals.
Asserted
means that a discrete signal is in active logic state.
—
Active low
signals change from logic level one to logic level zero.
—
Active high
signals change from logic level zero to logic level one.
Negated
means that an asserted discrete signal changes logic state.
—
Active low
signals change from logic level zero to logic level one.
—
Active high
signals change from logic level one to logic level zero.
LSB means
least significant bit
or
bits
, and MSB means
most significant bit
or
bits
. References to low and
high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or
0x
are
hexadecimal.
Watchdog
GPIO
LCD Controller
JTAG/ICE
CGM
(DPLLx2)
Timer 1 & 2
PWM
Standard
System I/O
Bootstrap
Connectivity
System Control
I2C
MMC/SD
SPI 1 and
SPI 2
UART 1
UART 2 & 3
USB Device
SmartCard I/F
Bluetooth
Accelerator
Memory Stick
Host Controller
SSI/I2S 1 & 2
Analog Signal
Processor
Human Interface
Video Port
Multimedia
Accelerator
Multimedia
Power
Control
RTC
Bus
Control
DMAC
(11 Chnl)
Interrupt
Controller
VMMU
CPU Complex
I Cache
AIPI 1
AIPI 2
D Cache
eSRAM
(128K)
EIM &
SDRAMC
ARM9TDMI
MC9328MX1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MXLVP20R2 | 功能描述:處理器 - 專門應用 DRAGONBALL MXL 225 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MXS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Advance Information |
| MC9328MXSCVF10 | 制造商:Rochester Electronics LLC 功能描述:REDUCED FEATURE I.MXL - Bulk 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
| MC9328MXSCVF10(R2) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Advance Information |
| MC9328MXSCVF10R2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Advance Information |
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