參數(shù)資料
型號(hào): MC9328MXL20
廠(chǎng)商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, MICROPROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁(yè)數(shù): 48/84頁(yè)
文件大?。?/td> 1492K
代理商: MC9328MXL20
52
MC9328MXL Advance Information
MOTOROLA
Specifications
T7
End of OE to beginning of HSYN
1
HWAIT1+1
Ts
T8
SCLK to valid LD data
-3
3
ns
T9
End of HSYN idle2 to VSYN edge
(for non-display region)
22
Ts
T9
End of HSYN idle2 to VSYN edge
(for Display region)
11
Ts
T10
VSYN to OE active (Sharp = 0),
when VWAIT2 = 0
11
Ts
T10
VSYN to OE active (Sharp = 1)
when VWAIT2 = 0
22
Ts
Note:
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 42, all 3 signals are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 42, SCLK
is always active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
Table 15. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
Minimum
Corresponding Register Value
Unit
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