參數(shù)資料
型號(hào): MC9328MXL20
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, MICROPROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù): 44/84頁
文件大?。?/td> 1492K
代理商: MC9328MXL20
Specifications
MOTOROLA
MC9328MXL Advance Information
49
3.9 SPI Timing Diagrams
To utilize the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as
a master, two control signals are used for data transfer rate control: the SS signal (output) and the
SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2
Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for
either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1
Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS
becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as
well as to increment the data FIFO. Figure 36 through Figure 40 show the timing relationship of the master
SPI using different triggering mechanisms.
.
Figure 36. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
Figure 37. Master SPI Timing Diagram Using SPI_RDY Level Trigger
Figure 38. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
Figure 39. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
1
2
3
5
4
SS
SPIRDY
SCLK, MOSI, MISO
SS
SPIRDY
SCLK, MOSI, MISO
SS (output)
SS (input)
SCLK, MOSI, MISO
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