參數(shù)資料
型號(hào)： MC9328MXL15
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, MICROPROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁(yè)數(shù)： 6/84頁(yè)
文件大?。?/td> 1492K
代理商： MC9328MXL15
14
MC9328MXL Advance Information
MOTOROLA
Specifications
3.6 DPLL Timing Specifications
Parameters of the DPLL are given in Table 8. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 8. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
Reference clock freq range
Vcc = 1.8V
5
—
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
—
30
MHz
Double clock freq range
Vcc = 1.8V
80
—
220
MHz
Pre-divider factor (PD)
—
1
—
16
—
Total multiplication factor
(MF)
Includes both integer
and fractional parts
5—
15
—
MF
integer part
—5
—
15
—
MF
numerator
Should be less than the
denominator
0
—
1022
—
MF
denominator
—
1
—
1023
—
Pre-multiplier lock-in time
—
312.5
nsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-mult lock-in
time)
250
280
(56
s)
300
Tref
Freq lock-in time after
partial reset
FOL mode for non-integer MF
(does not include pre-mult lock-in
time)
220
250
(~50
s)
270
Tref
Phase lock-in time after
full reset
FPL mode and integer MF (does
not include pre-mult lock-in time)
300
350
(70
s)
400
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does
not include pre-mult lock-in time)
270
320
(64
s)
370
Tref
Freq jitter (p-p)
—
0.005
(0.01%)
0.01
2Tdck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
—
1.0
(10%)
1.5
ns
Power supply voltage
—
1.8
—
2.5
V
Power dissipation
FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
——
4
mW
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