參數(shù)資料
型號(hào)： MC9328MXL15
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, MICROPROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁(yè)數(shù)： 50/84頁(yè)
文件大小： 1492K
代理商： MC9328MXL15
54
MC9328MXL Advance Information
MOTOROLA
Specifications
3.11.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 44. The symbols for Figure 44 through Figure 48
are defined in Table 17.
Figure 44. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 45, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods NRC and NCC.
Table 17. State Signal Parameters for Figure 44 through Figure 48
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit
(Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC
Cyclic redundancy check bits (7 bits)
E
End bit (1)
SET_RCA Timing
Identification Timing
Host Command
CID/OCR
NID cycles
CMD
Content
S T
E Z
Z S T
Content
Z Z
******
CRC
Z
Host Command
CID/OCR
NCR cycles
CMD
Content
S T
E Z
Z S T
Content
Z Z
******
CRC
Z
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