參數(shù)資料
型號： MC705JP7CPE
廠商： Freescale Semiconductor
文件頁數(shù)： 163/164頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 224 BYTES RAM 28PDIP
標(biāo)準(zhǔn)包裝： 13
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.600"，15.24mm）
包裝： 管件
Simple Synchronous Serial Interface
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
98
Freescale Semiconductor
to determine the source of the interrupt and will vector to the reset vector
as a default.
SPE — Serial Peripheral Enable Bit
The SPE bit switches the port B interface such that SDO/PB5 is the serial data output, SDI/PB6 is the
serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock output in the
master mode. The port B DDR and data registers can be manipulated as usual, but these actions will
not affect the transmitted or received data. The SPE bit is readable and writable at any time, but
clearing the SPE bit while a transmission is in progress will 1) abort the transmission, 2) reset the serial
bit counter, and 3) convert port B to a general-purpose I/O port. Reset clears the SPE bit.
1 = Serial peripheral enabled (port B I/O disabled)
0 = Serial peripheral disabled (port B I/O enabled)
LSBF — Least Significant Bit First Bit
The LSBF bit controls the format of the transmitted and received data to be transferred LSB or MSB
first. Reset clears this bit.
1 = LSB transferred first
0 = MSB transferred first
MSTR — Master Mode Select Bit
The MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing to the
SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon the
divider of the oscillator frequency selected by the SPR0:1 bits. When the device is in master mode, the
SDO and SDI pins do not change function. These pins behave exactly the same in both the master
and slave modes. The MSTR bit is readable and writable at any time regardless of the state of the SPE
bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the
MSTR bit, placing the SIOP subsystem in slave mode.
1 = SIOP set up as master, SCK is an output
0 = SIOP set up as slave, SCK is an input
SPIR — Serial Peripheral Interrupt Reset Bit
The SPIR bit is a write-only control to reset the SPIF flag bit in the SSR. Reading the SPIR bit will return
a logic 0.
1 = Reset the SPIF flag bit
0 = No effect
CPHA — Clock Phase Bit
The CPHA bit controls the clock timing and phase in the SIOP. Data is changed on the falling edge of
SCK and data is captured (read) on the rising edge of SCK. This bit is cleared by reset.
1 = SCK is idle low
0 = SCK is idle high
SPR0:1 — Serial Peripheral Clock Rate Select Bits
The SPR0 and SPR1 bits select one of four clock rates given in Table 9-1 to be supplied on the
PB7/SCK pin when the device is configured with the SIOP as a master (MSTR = 1). The fastest rate
is when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared by reset, which
places the SIOP clock selection at the slowest rate.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC705JP7CPE 制造商:Freescale Semiconductor 功能描述:IC 8BIT MCU 68HC05 2.1MHZ DIP-28
MC705K1CP 制造商:Motorola Inc 功能描述:16 PIN DIP INTEGRATED CIRCUIT
MC705L16CFUE 功能描述:8位微控制器 -MCU 8B MCU W/ EPROM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC705P6ACDWE 功能描述:8位微控制器 -MCU MCU 176 BYTES RAM A/D RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC705P6ACDWE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
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