參數(shù)資料
型號： MC68HC705C9ACP
廠商： Freescale Semiconductor
文件頁數(shù)： 89/118頁
文件大?。?/td> 0K
描述： IC MCU 2.1MHZ 16K OTP 40-DIP
標準包裝： 9
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SCI，SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 24
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： OTP
RAM 容量： 352 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
Serial Peripheral Interface (SPI)
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
72
Freescale Semiconductor
Figure 10-1. Data Clock Timing Diagram
10.3.1 Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an output in a slave device. It is one
of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO
line of a slave device is placed in the high-impedance state if the slave is not selected.
10.3.2 Master Out Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an input in a slave device. It is one
of the two lines that transfer serial data in one direction with the most significant bit sent first.
10.3.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out of the device through its MOSI
and MISO lines. The master and slave devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input
on a slave device.
As shown in Figure 10-1, four possible timing relationships may be chosen by using control bits CPOL
and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the MOSI line a half cycle before the clock
edge (SCK), in order for the slave device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device,
SPR0 and SPR1 have no effect on the operation of the SPI.
10.3.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to be low prior to data transactions
and must stay low for the duration of the transaction.The SS line on the master must be tied high. In
master mode, if the SS pin is pulled low during a transmission, a mode fault error flag (MODF) is set in
MSB
5
3
64
21
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
MISO/MOSI
SCK
SS
CPOL = 0
CPHA = 0
CPOL = 0
CPHA = 1
CPOL = 1
CPHA = 1
CPOL = 1
CPHA = 0
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相關代理商/技術參數(shù)
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MC68HC705C9ACPE 制造商:Freescale Semiconductor 功能描述:
MC68HC705C9AFNE 功能描述:8位微控制器 -MCU 8B MCU 352 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HC705C9AVFNE 功能描述:8位微控制器 -MCU 8B MCU 352 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HC705E6CDW 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述:
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