參數(shù)資料
型號: MC68HC08QY2CDTE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝: 0.65 MM PITCH, LEAD FREE, TSSOP-16
文件頁數(shù): 49/176頁
文件大?。?/td> 1124K
代理商: MC68HC08QY2CDTE
Development Support
MC68HC08QY/QT Family Data Sheet, Rev. 2
142
Freescale Semiconductor
Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors.
15.3.1.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
Figure 15-11. Monitor Data Format
15.3.1.4 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
Figure 15-12. Break Transaction
15.3.1.5 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external or internal oscillator
and the state of the appropriate pins as shown in Table 15-1.
Table 15-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the
bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in
forced monitor mode, the effective baud rate is the bus frequency divided by 335.
15.3.1.6 Commands
The monitor ROM firmware uses these commands:
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
Table 15-2. Mode Difference
Modes
Functions
Reset
Vector High
Reset
Vector Low
Break
Vector High
Break
Vector Low
SWI
Vector High
SWI
Vector Low
User
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
BIT 5
START
BIT
BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2
BIT 3
BIT 4
BIT 7
BIT 0
BIT 6
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
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