參數(shù)資料
型號： MC68HC08QY2CDTE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.65 MM PITCH, LEAD FREE, TSSOP-16
文件頁數(shù)： 138/176頁
文件大小： 1124K
代理商： MC68HC08QY2CDTE
Central Processor Unit (CPU)
MC68HC08QY/QT Family Data Sheet, Rev. 2
64
Freescale Semiconductor
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 6)
Source
Form
Operation
Description
Effect
on CCR
Addre
s
Mode
Op
co
de
Op
era
n
d
Cyc
les
VH I N Z C
ADC #opr
ADC opr
ADC opr,X
ADC ,X
ADC opr,SP
Add with Carry
A
← (A) + (M) + (C)
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
ADD #opr
ADD opr
ADD opr,X
ADD ,X
ADD opr,SP
Add without Carry
A
← (A) + (M)
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
AIS #opr
Add Immediate Value (Signed) to SP
SP
← (SP) + (16 M)
–––– –– IMM
A7
ii
2
AIX #opr
Add Immediate Value (Signed) to H:X
H:X
← (H:X) + (16 M)
–––– –– IMM
AF
ii
2
AND #opr
AND opr
AND opr,X
AND ,X
AND opr,SP
Logical AND
A
← (A) & (M)
0 – –
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Arithmetic Shift Left
(Same as LSL)
––
DIR
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
4
1
4
3
5
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,SP
Arithmetic Shift Right
––
DIR
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
4
1
4
3
5
BCC rel
Branch if Carry Bit Clear
PC
← (PC) + 2 + rel ? (C) = 0
–––– –– REL
24
rr
3
BCLR n, opr
Clear Bit n in M
Mn
← 0
–––– ––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
4
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC
← (PC) + 2 + rel ? (C) = 1
–––– –– REL
25
rr
3
BEQ rel
Branch if Equal
PC
← (PC) + 2 + rel ? (Z) = 1
–––– –– REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC
← (PC) + 2 + rel ? (N
⊕ V) = 0
–––– –– REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC
← (PC) + 2 + rel ? (Z) | (N
⊕ V) = 0 –––– –– REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC
← (PC) + 2 + rel ? (H) = 0
–––– –– REL
28
rr
3
BHCS rel
Branch if Half Carry Bit Set
PC
← (PC) + 2 + rel ? (H) = 1
–––– –– REL
29
rr
3
BHI rel
Branch if Higher
PC
← (PC) + 2 + rel ? (C) | (Z) = 0
–––– –– REL
22
rr
3
C
b0
b7
0
b0
b7
C
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