參數(shù)資料
型號： MC68HC08QY2CDTE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.65 MM PITCH, LEAD FREE, TSSOP-16
文件頁數(shù)： 113/176頁
文件大?。?/td> 1124K
代理商： MC68HC08QY2CDTE
Registers
MC68HC08QY/QT Family Data Sheet, Rev. 2
Freescale Semiconductor
41
stop mode (if ACLKEN is clear), ADCLK is written, or until ADCSC is written again. If stop is entered
(with ACLKEN low), continuous conversions will cease and can be restarted only with a write to
ADCSC. Any write to ADCSC with ADCO set and the ADCH bits not all 1s will abort the current
conversion and begin continuous conversions.
If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th
of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in
long-sample mode (ADLSMP = 1).
When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADCSC
is written (assuming the ADCH[4:0] bits do not decode all 1s).
1 = Continuous conversion following a write to ADCSC
0 = One conversion following a write to ADCSC
ADCH[4:0] — Channel Select Bits
The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input
channels are detailed in Table 3-2. The successive approximation converter subsystem is turned off
when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and
isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will
prevent an additional, single conversion from being performed. It is not necessary to set the channel
select bits to all 1s to place the ADC10 in a low-power state, however, because the module is
automatically placed in a low-power state when a conversion completes.
Table 3-2. Input Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select(1)
1. If any unused or reserved channels are selected, the resulting conversion will
be unknown.
00000
AD0
00001
AD1
00010
AD2
00011
AD3
00100
AD4
00101
AD5
00110
Unused
Continuing through
Unused
11001
Unused
11010
BANDGAP REF(2)
2. Requires LVI to be powered (LVIPWRD = 0, in CONFIG1)
11011
Reserved
11100
Reserved
11101
VREFH
11110
VREFL
11111
Low-power state
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