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參數(shù)資料
| 型號： | MC68HC08QT2CDWE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | LEAD FREE, EIAJ, SOIC-8 |
| 文件頁數(shù)： | 165/176頁 |
| 文件大小： | 1124K |
| 代理商： | MC68HC08QT2CDWE |
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Functional Description
MC68HC08QY/QT Family Data Sheet, Rev. 2
Freescale Semiconductor
89
11.3.1 Internal Signal Definitions
The following signals and clocks are used in the functional description and figures of the OSC module.
11.3.1.1 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and disables the XTAL oscillator
circuit, the RC oscillator, or the internal oscillator in stop mode. OSCENINSTOP in the configuration
register can be used to override this signal.
11.3.1.2 XTAL Oscillator Clock (XTALCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may
depend on the crystal and other external factors. The frequency of XTALCLK can be unstable at start up.
11.3.1.3 RC Oscillator Clock (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the
external R (REXT) and internal C. Figure 11-3 shows only the logical relation of RCCLK to OSC1 and may
not represent the actual circuitry.
11.3.1.4 Internal Oscillator Clock (INTCLK)
INTCLK is the internal oscillator output signal. INTCLK is software selectable to be nominally 12.8 MHz,
8.0 MHz, or 4.0 MHz. INTCLK can be digitally adjusted using the oscillator trimming feature of the
OSCTRIM register (see 11.3.2.1 Internal Oscillator Trimming).
11.3.1.5 Bus Clock Times 4 (BUSCLKX4)
BUSCLKX4 is the same frequency as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is
driven to the SIM module and is used during recovery from reset and stop and is the clock source for the
COP module.
11.3.1.6 Bus Clock Times 2 (BUSCLKX2)
The frequency of this signal is equal to half of the BUSCLKX4. This signal is driven to the SIM for
generation of the bus clocks used by the CPU and other modules on the MCU. BUSCLKX2 will be divided
by two in the SIM. The internal bus frequency is one fourth of the XTALCLK, RCCLK, or INTCLK
frequency.
11.3.2 Internal Oscillator
The internal oscillator circuit is designed for use with no external components to provide a clock source
with a tolerance of less than ±25% untrimmed. An 8-bit register (OSCTRIM) allows the digital adjustment
to a tolerance of
Δ
TRIM_ACC. See the oscillator characteristics in the Electrical section of this data sheet.
The internal oscillator is capable of generating clocks of 12.8 MHz, 8.0 MHz, or 4.0 MHz (INTCLK)
resulting in a bus frequency (INTCLK divided by 4) of 3.2 MHz, 2.0 MHz, or 1.0 MHz respectively. The
bus clock is software selectable and defaults to the 1.0-MHz bus out of reset. Users can increase the bus
frequency based on the voltage range of their application.
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