參數(shù)資料
型號: MC68HC08QT2CDWE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝: LEAD FREE, EIAJ, SOIC-8
文件頁數(shù): 121/176頁
文件大?。?/td> 1124K
代理商: MC68HC08QT2CDWE
Registers
MC68HC08QY/QT Family Data Sheet, Rev. 2
Freescale Semiconductor
49
AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears
AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE
KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 9.8.2 Keyboard Interrupt Enable
4.6.4 Configuration Register 2
The configuration register 2 (CONFIG2), is used to allow the bus clock source to run in STOP. In this case,
the clock, BUSCLKX2 will be used to drive the AWU request generator.
OSCENINSTOP — Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the bus clock source (BUSCLKX2) to generate clocks for the
AWU in stop mode. See 11.8.1 Oscillator Status and Control Register for information on enabling the
external clock sources.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
NOTE
IRQPUD, IRQEN, and RSTEN bits are not used in conjuction with the auto
wakeup feature. To see a description of these bits, see Chapter 5
4.6.5 Configuration Register 1
The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be
based on the COPRS bit along with the clock source for the AWU.
Bit 7
6543
2
1
Bit 0
Read:
IRQPUD
IRQEN
RRR
R
OSCENINSTOP
RSTEN
Write:
Reset:
00000
0
Figure 4-5. Configuration Register 2 (CONFIG2)
Bit 7
654321
Bit 0
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVITRIP
SSREC
STOP
COPD
Write:
Reset: POR:
0
U
0
U = Unaffected
Figure 4-6. Configuration Register 1 (CONFIG1)
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