參數(shù)資料
型號(hào)： MC68HC05E16CFB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16256 bytes of user ROM, 320bytes of EPROM and 352 bytes of RAM
中文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁(yè)數(shù)： 32/96頁(yè)
文件大?。?/td> 3045K
代理商： MC68HC05E16CFB
Freescale
5-2
MC68HC05SR3
RESETS AND INTERRUPTS
5
5.1.3
Low Voltage Reset (LVR)
When the LVR function is enabled, an internal reset is generated if the supply voltage, VDD, drops
below VLVR. (See Section 11 for value of VLVR).
This LVR function is enabled by setting the LVRE bit in the Miscellaneous Control Register.
LVRE — Low Voltage Reset Enable
1 (set)
–
Low Voltage Reset function enabled.
0 (clear) –
Low Voltage Reset function disabled.
Note:
The LVR function should not be enabled when operating VDD=3V.
5.2
INTERRUPTS
The MC68HC05SR3 MCU can be interrupted by different sources – four maskable hardware
interrupt and one non-maskable software interrupt:
Software Interrupt Instruction (SWI)
External signal on IRQ pin
External signal on IRQ2 pin
TImer Overflow
Keyboard
If the interrupt mask bit (I-bit) in the Condition Code Register (CCR) is set, all maskable interrupts
are disabled. Clearing the I-bit enables interrupts.
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and
executed. Table 5-1 shows the relative priority of all the possible interrupt sources. Figure 5-2
shows the interrupt processing flow.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Miscellaneous Control Register
$0C
KBIE
KBIC
INTO
INTE LVRE
SM
IRQ2F IRQ2E 0001 0000
TPG
36
05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM
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