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System Integration Module (SIM60)
6-38
MC68360 USER’S MANUAL
PIV7–PIV0—Periodic Interrupt Vector
These bits contain the value of the vector generated during an interrupt acknowledge cy-
cle in response to an interrupt from the PIT. When the SIM60 responds to the interrupt
acknowledge cycle, the periodic interrupt vector from the PICR is placed on the bus. This
vector number is multiplied by 4 to form the vector offset, which is added to the VBR in
the CPU32+ to obtain the address of the vector.
6.9.3.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for
prescaling the SWT and PIT as well as the count value for the PIT. This register can be read
or written at any time. Bits 15–10 are not implemented and always return zero when read.
A write does not affect these bits.
SUPERVISOR ONLY
SWP—Software Watchdog Prescaler Control
rising edge of reset.
0 = SWT clock is not prescaled.
1 = SWT clock is prescaled by a value of 512.
PTP—Periodic Timer Prescaler Control
This bit contains the prescaler control for the PIT. The PTP reset value is the inverse of
the MODCK1 pin state on the rising edge of reset.
0 = PIT clock is not prescaled.
1 = PIT clock is prescaled by a value of 512.
PITR7–PITR0—Periodic Interrupt Timer Register
These bits contain the remaining bits of the PITR count value for the PIT. A zero value
turns off the PIT. These bits may be written at any time to modify the PIT count value.
Table 6-6. Periodic Interrupt Request Level Encoding
PIRQL2
PIRQL1
PIRQL0
Interrupt Request Level
0
PIT Disabled
0
1
Interrupt Request Level 1
0
1
0
Interrupt Request Level 2
0
1
Interrupt Request Level 3
1
0
Interrupt Request Level 4
1
0
1
Interrupt Request Level 5
1
0
Interrupt Request Level 6
1
Interrupt Request Level 7
15
14
13
12
11
10
9876543210
0
00000
SWP
PTP
PITR7
PITR6
PITR5
PITR4
PITR3
PITR2
PITR1
PITR0
RESET:
0
00000
MODCK
1
MODCK
1
00000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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