參數(shù)資料
型號： MC56F8345MFG60
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 56F8345 16-bit Hybrid Controller
中文描述： 0-BIT, 240 MHz, OTHER DSP, PQFP128
封裝： 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128
文件頁數(shù)： 110/148頁
文件大小： 1420K
代理商： MC56F8345MFG60
110
56F8345 Technical Data
Preliminary
6.8 Stop and Wait Mode Disable Function
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For
lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly
before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut
down, the 56800E system clock must be set equal to the oscillator output.
Some applications require the 56800E STOP and WAIT instructions to be disabled. To disable
those instructions, write to the SIM control register (SIM_CONTROL), described in
Section 6.5.1
SIM Control Register (SIM_CONTROL)
. This procedure can be on either a permanent or
temporary basis. Permanently assigned applications last only until their next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin
and the Power-On Reset (POR). The two synchronous sources are the software reset, which is
generated within the SIM itself by writing to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is
sequenced to permit proper operation of the device. A POR reset is first extended for 2
21
clock
cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM
clocking is initiated. It is then followed by a 32 clock window in which peripherals are released to
implement Flash security, and, finally, followed by a 32 clock window in which the core is
initialized. After completion of the described reset sequence, application code will begin
execution.
Resets may be asserted asynchronously, but are always released internally on a rising edge of the
system clock.
D-FLOP
D
Q
C
D-FLOP
D
Q
C
R
56800E
STOP_DIS
Permanent
Disable
Reprogrammable Disable
Clock
Select
RESET
Note: Wait disable circuit is similar
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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參數(shù)描述
MC56F8345MFGE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz/60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8345VFG60 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8345VFGE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8346 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8346EVM 制造商:Freescale Semiconductor 功能描述:Tools Development kit Kit Contents:Inst
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