參數(shù)資料
型號: MC33121
廠商: Motorola, Inc.
英文描述: LOW VOLTAGE SUBSCRIBER LOOP INTERFACE CIRCUIT
中文描述: 低電壓用戶環(huán)路接口電路
文件頁數(shù): 12/32頁
文件大?。?/td> 570K
代理商: MC33121
MC33121
12
MOTOROLA
FUNCTIONAL DESCRIPTION
Introduction
The MC33121 is a solid state SLIC (Subscriber Line Inter-
face Circuit) which provides the interface between the two
wire telephone line and the four wire side of a Central Office
or PBX. Most of the BORSCHT functions are provided, spe-
cifically:
B
attery feed of the loop current to the line, with pro-
grammable maximum current for short lines and battery
feed resistance for long lines.
O
vervoltage protection through internal clamp diodes
and external resistors and diodes.
S
upervision, in that hook status is indicated in the pres-
ence of
30 k
leakage, and regardless of whether or
not the circuit is powered down intentionally by the Cen-
tral Office or PBX. Fault conditions are detected and in-
dicated to the system. Dialing (pulse and DTMF)
information is passed through the MC33121 to the 4–wire
side.
H
ybrid function, in that the MC33121 is a 2–to–4–wire
converter. Transmit, receive, return loss, and transhybrid
gains are independently adjustable.
Thy MC33121 does not provide ring insertion, ring trip, dig-
ital coding/decoding of the speech signals, nor test functions.
These must be provided external to this device.
The MC33121 controls two external transistors (one NPN
and one PNP) through which the loop current flows. By ap-
propriate circuit design, the power dissipation (which can
exceed 3.0 W under certain worst case conditions) is approx-
imately equally distributed among the two transistors and the
IC, thereby lowering junction temperatures and increasing
long term reliability. In most situations, heatsinks will not be
required.
The MC33121 incorporates critical sense resistors inter-
nally, which are trimmed for optimum performance. With this
technique, the external resistors on the two wire side, which
generally must be high wattage for transient protection rea-
sons, can be non–precision.
Longitudinal balance is tested to a minimum of 58 dB @
1.0 kHz (refer to Electrical Characteristics and Figure 2) for
both the two–wire and four–wire side, and typically measures
in the mid–60s. The longitudinal current capability is tested to
a minimum of 8.5 mArms per side (refer to Electrical Charac-
teristics and Figure 2) at a loop current of 20 mA.
Following is a description of the individual sections. Fig-
ure 4 is the reference schematic.
DC Loop Current
The DC loop current is determined by the battery voltage
(VEE), the load resistance across Tip and Ring, and the resis-
tor at RFO. Varying the 4 resistors RS and RC will influence
the loop current a small amount (< 5%). The curves of Fig-
ures 5 to 7 indicate the loop current versus loop resistance,
different values of RRF, and for various values of VEE. The
graphs represent performance at TA = 25
°
C and after the IC
had reached a steady state temperature (> 5 minutes).
+
+
+
+
Figure 27. DC Loop Current Path
VCC
EP
BP
CP
TSI
RSI
CN
BN
EN
VEE
ILOOP
RP
1.0 k
9.1 k
9.1 k
1.0 k
ILOOP
100
RING
TIP
RL
–24 V
IA = IRXI
30
3060
31 k
100
IA
VDD
ICP
ICN
30
3060
5.0
0.8 V
31 k
100
IA
VDD
VQB
12.4 k
ICP
ICN
3
VAG
ANALOG
GROUND
IRXI
RXI
RRF
RFO
VQB
10
μ
F
RP
100
MC33121
CURRENT
MIRROR
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