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參數(shù)資料
| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 65/128頁(yè) |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
41
3.5.15 External Bus Interface in Low-Power Stop Mode
In low-power stop mode (LPSTOP), the EBI controls the state of the external bus pins, based on the
state of the EBR pin. If EBR is low, the SLIM does not drive the address, address/data, AS, DS, R/W,
SIZE, and ALE pins. If EBR is high, the SLIM drives the address, address/data, AS, DS, R/W, and SIZE
pins to their last known state. EBR does not need to be held low during the duration of LPSTOP. Only
a short pulse (25 ns) is required.
3.6 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. This MCU per-
forms resets with a combination of hardware and software. The SLIM determines whether a reset is val-
id, asserts control signals, performs basic system configuration and boot ROM selection based on
hardware mode-select inputs, then passes control to the CPU16.
Reset occurs when an active low logic level on the RESET pin is clocked into the SLIM. Resets are gat-
ed by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous re-
set can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If
there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are
clocked to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
The reset status register contains a bit for each reset source in the MCU. A bit set to one indicates what
type of reset has occurred. Only one bit in RSR will be set at any time. The reset status register is up-
dated by the reset control logic when the MCU comes out of reset. This register can be read at any time.
A write has no effect.
EXT — External Reset
Reset was caused by an external signal.
POW — Power-Up Reset
Reset was caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset was caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset was caused by the halt monitor.
LOC — Loss of Clock Reset
Reset was caused by loss of clock submodule frequency reference. This reset can only occur if the
RSTEN bit in the clock submodule is set and the VCO is enabled.
SYS — System Reset
Reset was caused by a CPU RESET instruction. The CPU16 has no RESET instruction, therefore, this
bit is not used on the MC68HC16V1 and always reads zero.
TST — Test Submodule Reset
Reset was caused by the test submodule.
RSR — Reset Status Register
$YFFA07
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
EXT
POW
SW
HLT
0
LOC
SYS
TST
RESET:
CURRENT STATE OF CORRESPONDING PINS
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