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參數(shù)資料
| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 38/128頁(yè) |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
17
The sub-module disable register (SMD) is used to disable sub-modules within the SLIM when they are
not in use. A sub-module is disabled when its corresponding bit is set to one. Disabling the sub-module
prevents it from being clocked, thereby placing the sub-module in its lowest power consumption state.
BRKEN — Breakpoint Enable
When enabled, this bit asserts BKPT on the IMB when any of the chip-select match signals is true, plac-
ing the CPU16 into background debug mode. This allows the user to breakpoint on addresses and con-
ditions specified in the chip-select registers.
0 = Breakpoint logic is disabled
1 = Breakpoint logic is enabled
CHIP SELECT — Chip-Select Disable
0 = Chip-select sub-module is enabled
1 = Chip-select sub-module is disabled
TEST —Test Disable
0 = Test sub-module is enabled
1 = Test sub-module is disabled
SYSPROT— System Protect Disable
Disabling the system protection sub-module prevents the software watchdog timer, real time clock,
prescaler, bus monitor, spurious interrupt monitor, and halt monitor from functioning.
0 = System protection sub-module is enabled
1 = System protection sub-module is disabled
The port/clock configuration shadow register (PCON) is a mask programmable register that determines
the default reset value of corresponding bits and fields in the port C, D, and E pin assignment registers,
as well as the default clock configuration. Refer to Table 10.
During reset, the specified configuration is loaded based on the information programmed in PCON at
mask time. Driving DRCD to a logic level zero when RESET is asserted overrides the configuration in
PCON for some port pin assignment bits and the clock select. This allows them to be configured from
outside the device by the state driven on certain SLIM pins during reset. Not all bits in the port pin as-
signment registers have corresponding shadow bits in PCON.
NOTE
PCON programming must be consistent with pin availability. If a pin does not exist
on the device, PCON bits should be programmed to configure the pin function as
digital I/O out of reset, since EBI operation can be affected by the presence or ab-
sence of these pins. Refer to Table 1 for the factory specified PCON value appro-
priate to the MCU package being used.
PCON — Port/Clock Configuration Shadow Register
$YFFA0E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PCON[13:11]
PCON[10:9]
PCON[8:7]
PCON[6:5]
PCON4 PCON3 PCON2 PCON1 PCON0
RESET:
USER SPECIFIED
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