參數(shù)資料
型號(hào): MC12U128DACA-2QC00
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Dual Voltage MultiMediaCard Specification
中文描述: 雙電壓多媒體卡規(guī)格
文件頁(yè)數(shù): 54/64頁(yè)
文件大?。?/td> 1385K
代理商: MC12U128DACA-2QC00
MultiMediaCard
TM
addressed group.
if the card has write protection
features, this command asks the
card to send the status of the write
protection bits.
*5
sets the address of the first erase
group within a range to be
selected for erase
sets the address of the last erase
group within a continuous range to
be selected for erase
erases all previously selected
sectors
Used to set/reset the password or
lock/unlock the card. The structure
of the data block is described in
chapter “Card lock/unlock
operation”. The size of the Data
Block is defined by the
SET_BLOCK_LEN command.
CMD30
Yes
[31:0] write protect
data address
R1
SEND_WRITE_
PROT
CMD31
CMD35
reserved
Yes
[31:0]
address
R1
TAG_ERASE_
GROUP_START
data
CMD36
Yes
[31:0]
address
data
R1
TAG_ERASE_
GROUP_END
CMD38
Yes
[31:0] stuff bits
R1b
ERASE
CMD39
CMD40
CMD41
CMD42
No
No
reserved
Yes
[31:0] stuff bits
R1b
LOCK/UNLOCK
CMD43…
CMD57
CMD58
CMD59
reserved
Yes
Yes
None
[31:0] stuff bits
[0:0] CRC option
R3
R1
READ_OCR
CRC_ON_OFF
Reads the OCR register of a card.
Turns the CRC option on or off. A
‘1’ in the CRC option bit will turn
the option on, a ‘0’ will turn it off.
CMD60
Notes :
No
1. The default block length is as specified in the CSD.
2. The data transferred must not cross a physical block boundary unless READ_BLK_MISALIGN is set in
the CSD.
3. R1b : R1 response with an optional trailing busy signal.
4. The data transferred must not cross a physical block boundary unless WRITE_BLK_MISALIGN is set in
the CSD.
5. 32 write protection bits (representing 32 write protect groups starting at the specified address) followed by
16 CRC bits are transferred in a payload format via the data line. The last (least significant) bit of the
protection bits corresponds to the first addressed group. If the addresses of the last groups are outside the
valid range, then the corresponding write protection bits shall be set to zero.
54
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