Semiconductor Components Industries, LLC, 2004
December, 2004 Rev. 6
1
Publication Order Number:
MC14049UB/D
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logiclevel conversion using only one
supply voltage, V
DD
. The inputsignal high level (V
IH
) can exceed the
V
DD
supply voltage for logiclevel conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOStoTTL/DTL
converters (V
DD
= 5.0 V, V
OL
0.4 V, I
OL
≥
3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
Features
High Source and Sink Currents
HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V
Meets JEDEC UB Specifications
V
IN
can exceed V
DD
Improved ESD Protection on All Inputs
PbFree Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
V
in
DC Supply Voltage Range
Input Voltage Range
(DC or Transient)
0.5 to +18.0
0.5 to +18.0
V
V
V
out
Output Voltage Range
(DC or Transient)
0.5 to V
DD
+0.5
±
10
V
I
in
Input Current
(DC or Transient) per Pin
mA
I
out
Output Current
(DC or Transient) per Pin
+45
mA
P
D
Power Dissipation, per Package (Note 1)
Plastic
SOIC
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8Second Soldering)
825
740
mW
T
A
T
stg
T
L
55 to +125
65 to +150
260
°
C
°
C
°
C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V
SS
pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this highimpedance circuit. For proper operation, the ranges V
SS
V
in
18 V and V
SS
V
out
V
DD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
MARKING
DIAGRAMS
16
1
PDIP16
P SUFFIX
CASE 648
MC14049UBCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
1
16
14049U
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC14049UB
ALYW
TSSOP16
DT SUFFIX
CASE 948F
14
049U
ALYW
1
16
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
*For additional information on our PbFree strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.