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參數(shù)資料
| 型號(hào)： | MC12439FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 155K |
| 代理商： | MC12439FN |
MC12439
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
375
Figure 4. Serial Test Clock Block Diagram
Table 3. DC Characteristics (VCC = 3.3 V ±5%)
Symbol
Characteristic
0
°C
25
°C
70
°C
Unit
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
0.8
V
IIN
Input Current
1.0
mA
IOH
Output HIGH Current1
FOUT, FOUT
1.
Maximum IOH spec implies the device can drive 25 impedance with the PECL outputs.
50
mA
Continuous
VOH
Output HIGH Voltage
TEST
2.5
V
IOH = –0.8mA
VOL
Output LOW Voltage
TEST
0.4
V
IOL = 0.8mA
VOH
Output HIGH Voltage2
FOUT, FOUT
2.
See APPLICATIONS INFORMATION for output level versus frequency information.
2.28
2.60
2.32
2.49
2.38
2.565
V
VCCO = 3.3V
3 4
3.
Output levels will vary 1:1 with VCC variation.
4.
50
to V
CC – 2.0V termination.
VOL
Output LOW Voltage2
FOUT, FOUT
1.35
1.67
1.35
1.67
1.35
1.70
V
VCCO = 3.3V
3 4
ICC
Power Supply Current
VCC
PLL_VCC
90
15
110
20
90
15
110
20
90
15
110
20
mA
Table 4. DC Characteristics (VCC = 5.0 V ±5%)
Symbol
Characteristic
0
°C
25
°C
70
°C
Unit
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VIH
Input HIGH Voltage
3.5
V
VIL
Input LOW Voltage
0.8
V
IIN
Input Current
1.0
mA
IOH
Output HIGH Current1
FOUT, FOUT
1.
Maximum IOH spec implies the device can drive 25 impedance with the PECL outputs.
50
mA
Continuous
VOH
Output HIGH Voltage
TEST
3.8
V
IOH = -0.8 mA
VOL
Output LOW Voltage2
TEST
2.
See APPLICATIONS INFORMATION for output level versus frequency information.
0.4
V
IOL = 0.8 mA
VOH
Output HIGH Voltage2
FOUT, FOUT
3.98
4.30
4.02
4.19
4.08
4.265
V
VCCO = 5.0 V
3 4
3.
Output levels will vary 1:1 with VCC0 variation.
4.
50
to V
CC – 2.0V termination.
VOL
Output LOW Voltage
FOUT, FOUT
3.05
3.37
3.05
3.37
3.05
3.40
V
VCCO = 5.0 V
3 4
ICC
Power Supply Current
VCC
PLL_VCC
90
15
110
20
90
15
110
20
90
15
110
20
mA
FDIV4
MCNT/2
LOW
FOUT
MCNT/2
FREF
HIGH
TEST
MUX
7
0
TEST
FOUT
(VIA ENABLE GATE)
N DIVIDE
(1, 2, 4, 8)
0
1
PLL 12439
LATCH
Reset
PLOAD
M COUNTER
SLOAD
T0
T1
T2
VCO
SHIFT
REG
12-BIT
DECODE
SDATA
SCLOCK
MCNT
FREF
SEL_CLK
T2=T1=1, T0=0: Test Mode (PLL bypass)
SCLOCK is selected, MCNT/2 is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOAD acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
Shift Reg. Out
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