參數(shù)資料
型號(hào)： MBM29DL161BE-90PBT
廠商： FUJITSU LTD
元件分類： PROM
英文描述： 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： PLASTIC, FBGA-48
文件頁(yè)數(shù)： 36/76頁(yè)
文件大?。?/td> 1145K
代理商： MBM29DL161BE-90PBT
MBM29DL16XTE/BE70/90
41
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the begining of the algorithm when it returns to determine
the status of the operation. (Refer to “(4) Toggle Bit Algorithm” in sFLOW CHART.)
Toggle Bit Status Table
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2 : Reading from the non-erase suspend sector address indicates logic “1” at the DQ2 bit.
RY/BY
Ready/Busy
The MBM29DL16XTE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL16XTE/BE are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to “(10) RY/BY Timing Diagram during Program/Erase
Operations” and “(11) RESET, RY/BY Timing Diagram” in sTIMING DIAGRAM for a detailed timing diagram.
The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to VCC ; multiples of devices may
be connected to the host system via more than one RY/BY pin in parallel.
Data Protection
The MBM29DL16XTE/BE are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Toggle*1
Erase-Suspend Read
(Erase-Suspended Sector)
11
Toggle
Erase-Suspend Program
DQ7
Toggle
1*2
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