參數(shù)資料
型號： MBM29DL161BE-90PBT
廠商： FUJITSU LTD
元件分類： PROM
英文描述： 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： PLASTIC, FBGA-48
文件頁數(shù)： 19/76頁
文件大小： 1145K
代理商： MBM29DL161BE-90PBT
MBM29DL16XTE/BE70/90
26
s FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL16XTE/BE have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A19 to A15) with zero latency.
The MBM29DL161TE/BE have two banks which contain
Bank 1 (8KB
× 8 sectors) and Bank 2 (64KB × 31 sectors).
The MBM29DL162TE/BE have two banks which contain
Bank 1 (8KB
× 8 sectors, 64KB × 3 sectors) and Bank 2 (64KB × 28 sectors).
The MBM29DL163TE/BE have two banks which contain
Bank 1 (8KB
× 8 sectors, 64KB × 7 sectors) and Bank 2 (64KB × 24 sectors).
The MBM29DL164TE/BE have two banks which contain
Bank 1 (8KB
× 8 sectors, 64KB × 15 sectors) and Bank 2 (64KB × 16 sectors).
The simultaneous operation can not execute multi-function mode in the same bank. “Simultaneous Operation
Table” shows combination to be possible for simultaneous operation. (Refer to “(8) Bank-to-bank Read/Write
Timing Diagram” in sTIMING DIAGRAM.)
*: By writing erase suspend command on the bank address of sector being erased, the erase operation becomes
suspended so that it enables reading from or programming the remaining sectors.
Read Mode
The MBM29DL16XTE/BE have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time (tOE) is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” to “L”.
Simultaneous Operation Table
Case
Bank 1 Status
Bank 2 Status
1
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode *
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode *
Read mode
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