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參數(shù)資料
| 型號： | MB9AF312LPMC1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 26/114頁 |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF312LPMC1 |
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19
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
8.4.2
Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design
solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to
the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly,
if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the
internal brown-out detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an
external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.
8.5
I/O Memory
The I/O space definition of the Atmel ATmega48PA/88PA/168PA is shown in Section 31. “Register Summary” on page 310.
All Atmel ATmega48PA/88PA/168PA I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by
the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the
I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction
set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be
used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within
the 64 location reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
8.5.1
General Purpose I/O Registers
The Atmel ATmega48PA/88PA/168PA contains three general purpose I/O registers. These registers can be used for storing
any information, and they are particularly useful for storing global variables and status flags. General purpose I/O registers
within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
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