- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45202 > MB9AF312LPMC1 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB9AF312LPMC1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 11/114頁(yè) |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF312LPMC1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
108
The general I/O port function is overridden by the output compare (OC1x) from the waveform generator if either of the
COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the data direction register
(DDR) for the port pin. The data direction register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x
value is visible on the pin. The port override function is generally independent of the waveform generation mode, but there
are some exceptions. Refer to Table 16-2 on page 116, Table 16-3 on page 117 and Table 16-4 on page 117 for details.
The design of the output compare pin logic allows initialization of the OC1x state before the output is enabled. Note that
some COM1x1:0 bit settings are reserved for certain modes of operation. See
The COM1x1:0 bits have no effect on the input capture unit.
16.8.1 Compare Output Mode and Waveform Generation
The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the
COM1x1:0 = 0 tells the waveform generator that no action on the OC1x register is to be performed on the next compare
match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 116. For fast PWM mode refer to
Table 16-3 on page 117, and for phase correct and phase and frequency correct PWM refer to Table 16-4 on page 117.
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.
16.9
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of
the waveform generation mode (WGM13:0) and compare output mode (COM1x1:0) bits. The compare output mode bits do
not affect the counting sequence, while the waveform generation mode bits do. The COM1x1:0 bits control whether the
PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits
control whether the output should be set, cleared or toggle at a compare match (See
For detailed timing information refer to Section 16.10 “Timer/Counter Timing Diagrams” on page 114.
16.9.1 Normal Mode
The simplest mode of operation is the normal mode (WGM13:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value
(MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter overflow flag (TOV1)
will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1
flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new
counter value can be written anytime.
The input capture unit is easy to use in normal mode. However, observe that the maximum interval between the external
events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt
or the prescaler must be used to extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the output compare to generate
waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB9AF312MPMC | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80 |
| MB9AF312LPMC | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 |
| MB9AF311NPMC | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100 |
| MB9AF316NPMC | RISC MICROCONTROLLER, PQFP100 |
| MB9AF314NPMC | RISC MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB9AF314LAPMC1-G-JNE2 | 制造商:FUJITSU 功能描述: |
| MB9AF314LAPMC-G-JNE2 | 制造商:Fujitsu 功能描述:Bulk |
| MB9AF314LAQN-G-AVE2 | 功能描述:ARM? Cortex?-M3 FM3 MB9A310A Microcontroller IC 32-Bit 40MHz 256KB (256K x 8) FLASH 64-QFN Exposed Pad (9x9) 制造商:cypress semiconductor corp 系列:FM3 MB9A310A 包裝:托盤 零件狀態(tài):有效 核心處理器:ARM? Cortex?-M3 核心尺寸:32-位 速度:40MHz 連接性:CSIO，I2C，LIN，UART/USART，USB 外設(shè):DMA，LVD，POR，PWM，WDT I/O 數(shù):51 程序存儲(chǔ)容量:256KB（256K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 容量:- RAM 容量:32K x 8 電壓 - 電源（Vcc/Vdd）:2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 9x12b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 105°C（TA） 封裝/外殼:64-VFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN 裸露焊盤（9x9） 標(biāo)準(zhǔn)包裝:260 |
| MB9AF314LPMC1-ESE1 | 制造商:FUJITSU 功能描述: |
| MB9AF314LPMC1-GE1 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。