參數(shù)資料
型號(hào)： MB91F345BPFT-GE1
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 12 X 12 MM, 1.20 MM HEIGHT, 0.40 MM PITCH, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 14/72頁(yè)
文件大?。?/td> 657K
代理商： MB91F345BPFT-GE1
MB91345 Series
21
Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated. In either case, the operations before and after an EIT are performed as specified as the device
is designed such that the recovery from the EIT is followed by correct re-processing.
The instruction just before the DIV0U/DIV0S instruction may cause the following operation, if a user interrupt
or NMI occurs, single-stepping is performed or a break is caused by a data event or emulator menu :
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as shown in (1) .
If the ORCCR/STILM/MOV Ri and PS instructions are executed to enable interruptions when a user interrupt
or NMI trigger even has occurred, the following operations are performed.
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the instructions shown above are executed and the PS register is updated
to the same value as shown in (1) .
About watchdog timer
MB91345 series has an internal function called “watchdog timer”. This function monitors a program to perform
the reset defer operation within a certain period of time. The watchdog timer resets the CPU if the program
runs out of controls and the reset defer operation is not executed. Thus, once enabled, the watchdog timer
will be up and running until it resets the CPU. However, with one exception, the watchdog timer automatically
defers a reset timing under the condition in which the CPU stops program execution. Refer to the hardware
manual. If the system runs out of control and develops the above condition, a watchdog reset may not be
generated. In that case, please reset (INIT) from external INIT terminal.
Note on using the A/D converter
MB91345 series has an internal A/D converter. The AVCC pin should not be supplied with higher voltage than
VCC pin.
Software reset in synchronous mode
When using the software reset in the synchronous mode, the following two conditions should be satisfied
before setting “0” to the SRST bit in STCR (Standby control register) .
Set the interrupt enable flag (I-Flag) to interrupt disable (I-Flag = 0) .
Do not use NMI.
Debug control when using ICE
Single-stepping of the RETI instruction
If an interrupt occurs frequently during single stepping, only the relevant interrupt processing routine is executed
repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from
being executed. Do not single-step the RETI instruction for escape. When the debugging of the relevant
interrupt routine no longer requires, perform debugging with that interrupt disabled.
About operand break
Do not apply a data event break to access to the area containing the address of a stack pointer.
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