參數(shù)資料
型號: MB91F267NAPMC-GSE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 22/53頁
文件大?。?/td> 0K
描述: IC MCU FLASH 128KB FLASH 64LQFP
標準包裝: 1
系列: FR MB91265A
核心處理器: FR60Lite RISC
芯體尺寸: 32-位
速度: 33MHz
連通性: CAN,UART/USART
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: 865-1102-ND - BOARD EVAL RS232 100QFP
其它名稱: 865-1091
31
8183F–AVR–06/12
ATtiny24A/44A/84A
6.5
Register Description
6.5.1
OSCCAL – Oscillator Calibration Register
Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in Table 20-2 on page 175. The application software can write this register to change
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 20-
2 on page 175. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the
ical frequencies.
To ensure stable operation of the MCU the calibration value should be changed in small. A vari-
ation in frequency of more than 2% from one cycle to the next can lead to unpredicatble
behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to
ensure that the MCU is kept in Reset during such changes in the clock frequency.
6.5.2
CLKPR – Clock Prescale Register
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
Bits 6:4 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A/84A and will always read as zero.
Bit
765
432
10
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/Write
R/W
Initial Value
Device Specific Calibration Value
Bit
7
6
5
4
32
10
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
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