參數(shù)資料
型號: MB91F267NAPMC-GSE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 15/53頁
文件大?。?/td> 0K
描述: IC MCU FLASH 128KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91265A
核心處理器: FR60Lite RISC
芯體尺寸: 32-位
速度: 33MHz
連通性: CAN,UART/USART
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: 865-1102-ND - BOARD EVAL RS232 100QFP
其它名稱: 865-1091
25
8183F–AVR–06/12
ATtiny24A/44A/84A
6.1.2
I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
6.1.3
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
6.1.4
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
6.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Note:
1. For all fuses “1” means unprogrammed and “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down the selected clock source is used to time the start-up, ensuring sta-
ble Oscillator operation before instruction execution starts. When the CPU starts from reset,
there is an additional delay allowing the power to reach a stable level before commencing nor-
mal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time.
The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2.
Table 6-1.
Device Clocking Options
Device Clocking Option
CKSEL[3:0]
0000
Reserved
0001
0010
Reserved
0011
0100
Reserved
0101
Reserved
0111
1000-1111
Table 6-2.
Number of Watchdog Oscillator Cycles
Typ Time-out
Number of Cycles
4 ms
512
64 ms
8K (8,192)
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