參數(shù)資料
型號： MB91F267APMC-GE1
廠商： Fujitsu Semiconductor America Inc
文件頁數(shù)： 43/53頁
文件大?。?/td> 0K
描述： IC MCU FLASH 128KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝： 1
系列： FR MB91265A
核心處理器： FR60Lite RISC
芯體尺寸： 32-位
速度： 33MHz
連通性： UART/USART
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 49
程序存儲器容量： 128KB（128K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
其它名稱： 865-1092
50
8183F–AVR–06/12
ATtiny24A/44A/84A
9.3
Register Description
9.3.1
MCUCR – MCU Control Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
9.3.2
GIMSK – General Interrupt Mask Register
Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A and will always read as zero.
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT[11:8] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT[11:8] pins are enabled individually by the PCMSK1 Register.
Bit
765
432
10
BODS
PUD
SE
SM1
SM0
BODSE
ISC01
ISC00
MCUCR
Read/Write
R/W
Initial Value
0
Table 9-2.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
7
6
543
21
0
–
INT0
PCIE1
PCIE0
–
GIMSK
Read/Write
R
R/W
R/W1
R
Initial Value
0
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參數(shù)描述
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MB91F267NA 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers
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