參數(shù)資料
型號： MB91267NAPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LFQFP-64
文件頁數(shù)： 11/56頁
文件大?。?/td> 473K
代理商： MB91267NAPMC
MB91265A Series
19
■ NOTE ON DEBUGGER
Step execution of RETI command
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed
repeatedly after step execution.
This will prevent the main routine and low-interrupt-level programs from being executed.
Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine
no longer needs debugging.
Operand break
Do not apply a data event break to access to the area containing the address of a system stack pointer.
Execution in an unused area of flash memory
Accidentally executing an instruction in an unused area of flash memory (with data placed at 0xFFFF) prevents
breaks from being accepted.
To prevent this, the code event address mask function of the debugger should be used to cause a break when
accessing an instruction in an unused area.
Power-on debugging
All of the following three conditions must be satisfied when the power supply is turned off by power-on debugging.
(1) The time for the user power to fall from 0.9 VCC to 0.5 VCC is 25
s or longer.
Note : In a dual-power system, VCC indicates the external I/O power supply voltage.
(2) CPU operating frequency must be higher than 1 MHz.
(3) During execution of user program
Interrupt handler for NMI request (tool)
Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor
flag to be set only in response to a break request from the ICE is set, for example, by an adverse effect of noise
to the DSU pin while the ICE is not connected. Enable to use the ICE while adding this program.
Additional location
Next interrupt handler
Additional program
Interrupt source
: NMI request (tool)
Interrupt number
: #13 (decimal) , 0D (hexadecimal)
Offset
: 3C8H
Address TBR is default
: 000FFFC8H
STM
(R0, R1)
LDI
#B00H, R0;
: B00H is the address of DSU break factor register.
LDI
#0, R1
STB
R1, @R0
: Clear the break factor register.
LDM
(R0, R1)
RETI
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