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CHAPTER 15 I
2
C
15.1 Overview of the I
2
C
The I
2
C is a simple bidirectional bus consisting of two wires that transfer data among
devices. These two I
2
C bus interfaces allow internal devices requiring address data to
connect to one another with a minimum number of circuits, making it possible to
construct less expensive hardware using a fewer number of PCBs.
The I
2
C interface that supports Philips's I
2
C bus specification and Intel's SM bus
specification provides master/slave transmission and reception, arbitration lost
detection, slave address/general call address detection, generation and detection of
start/stop conditions, and buss error detection.
I
I
2
C Functions
The I
2
C interface is a simple structure bidirectional bus consisting of two wires: a serial data line
(SDA) and a serial clock line (SCL). Among the devices connected with these two wires,
information is transmitted to one another. By recognizing the unique address of each device, it
can operate as a transmitting or receiving device in accordance with the function of each device.
Among these devices, the master/slave relation is established.
The I
2
C interface can connect two or more devices to the bus provided the upper limit of the bus
capacitance does not exceed 400pF. It is a full-fledged multi-master bus equipped with collision
detection and communication adjustment procedures designed to avoid the destruction of data if
two or more masters attempt to start data transfer simultaneously.
A configuration example of the I
2
C interface is shown in Figure 15.1-1 "I
2
C Block Diagram".
The communication adjustment procedure permits only one master to control the bus when two
or more masters attempt to control the bus so that messages are not lost or the contents of
messages are not changed. Multi-master means that multiple masters attempt to control the
bus simultaneously without losing messages.