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參數(shù)資料
| 型號(hào)： | MAX9789CETJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUDIO 2W STER AB 32TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | DirectDrive® |
| 類型： | AB 類 |
| 輸出類型： | 2-通道（立體聲）帶立體聲耳機(jī) |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 2W x 2 @ 4 歐姆; 100mW x 2 @ 16 歐姆 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 特點(diǎn)： | 消除爆音，靜音，短路保護(hù)和熱保護(hù)，關(guān)機(jī) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFN-EP（5x5） |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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MAX9789/MAX9790
Windows Vista-Compliant, Stereo Class AB Speaker
Amplifiers and DirectDrive Headphone Amplifiers
20
______________________________________________________________________________________
Output Capacitor (C2)
The output capacitor value and ESR directly affect the
ripple at CPVSS. Increasing the value of C2 reduces
output ripple. Likewise, decreasing the ESR of C2
reduces both ripple and output resistance. Lower
capacitance values can be used in systems with low
maximum output power levels.
CPVDD Bypass Capacitor (C3)
The CPVDD bypass capacitor (C3) lowers the output
impedance of the power supply and reduces the
impact of the MAX9789/MAX9790’s charge-pump
switching transients. Bypass CPVDD with 1F, the same
value as C1, and place it physically close to the CPVDD
and CPGND pins.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance, as well as route heat away
from the device. Good grounding improves audio per-
formance, minimizes crosstalk between channels, and
prevents switching noise from coupling into the audio
signal. Connect PGND and GND together at a single
point on the PC board. Route PGND and all traces that
carry switching transients away from GND and the
traces and components in the audio signal path.
Connect C2 and C3 to the PGND plane. Connect PVSS
and CPVSS together at C2. Place the charge-pump
capacitors (C1, C2, and C3) as close as possible to
the device. Bypass PVDD with a 0.1F capacitor to
PGND. Place the bypass capacitors as close as possi-
ble to the device.
Use large, low-resistance output traces. As load imped-
ance decreases, the current drawn from the device out-
puts increase. At higher current, the resistance of the
output traces decrease the power delivered to the load.
For example, if 2W is delivered from the speaker output
to a 4Ω load through a 100mΩ trace, 49mW is con-
sumed in the trace. If power is delivered through a
10mΩ trace, only 5mW is consumed in the trace. Large
output, supply and GND traces also improve the power
dissipation of the device.
The MAX9789/MAX9790 thin QFN package features an
exposed thermal pad on its underside. This pad lowers
the package’s thermal resistance by providing a direct
heat conduction path from the die to the printed circuit
board. Connect the exposed thermal pad to GND by
using a large pad and multiple vias to the GND plane.
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