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| 型號： | MAX9789CETJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUDIO 2W STER AB 32TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | DirectDrive® |
| 類型： | AB 類 |
| 輸出類型： | 2-通道（立體聲）帶立體聲耳機(jī) |
| 在某負(fù)載時最大輸出功率 x 通道數(shù)量： | 2W x 2 @ 4 歐姆; 100mW x 2 @ 16 歐姆 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 特點(diǎn)： | 消除爆音，靜音，短路保護(hù)和熱保護(hù)，關(guān)機(jī) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFN-EP（5x5） |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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MAX9789/MAX9790
Windows Vista-Compliant, Stereo Class AB Speaker
Amplifiers and DirectDrive Headphone Amplifiers
18
______________________________________________________________________________________
Mono Speaker Configuration
The MAX9789 stereo BTL Class AB speaker amplifier
can be configured to drive a mono speaker. Rather
than combining the CODEC’s left- and right-input sig-
nals in a resistive network prior to one channel of the
speaker amplifier input, the transducer itself can be
connected to the BTL speaker amplifier output as
shown in Figure 6. When compared to the resistive net-
work implementation, the configuration in Figure 6 will:
1) Eliminate noise pickup by eliminating the high-
impedance node at the CODEC’s left- and right-
signal mixing point. SNR performance will be
improved as a result.
2) Eliminate gain error by eliminating any resistive
mismatch between the external resistance used to
sum the left and right signals and the MAX9789
internal resistance.
Power Dissipation and Heat Sinking
Under normal operating conditions, the MAX9789/
MAX9790 can dissipate a significant amount of power.
The maximum power dissipation for each package is
given in the
Absolute Maximum Ratings section under
Continuous Power Dissipation, or can be calculated by
the following equation:
where TJ(MAX) is +150°C, TA is the ambient tempera-
ture, and
θJA is the reciprocal of the derating factor in
°C/W as specified in the
Absolute Maximum Ratings
section. For example,
θJA for the 32-pin TQFN-EP pack-
age is +40.2°C/W for a multilayer PC board.
Output Power (Speaker Amplifier)
The increase in power delivered by the BTL configura-
tion directly results in an increase in internal power dis-
sipation over the single-ended configuration. The
maximum power dissipation for a given VDD and load is
given by the following equation:
If the power dissipation for a given application exceeds
the maximum allowed for a given package, either reduce
VDD, increase load impedance, decrease the ambient
temperature, or add heat sinking to the device. Large
output, supply, and ground PC board traces improve the
maximum power dissipation in the package.
Thermal-overload protection limits total power dissipa-
tion in these devices. When the junction temperature
exceeds +150°C, the thermal-protection circuitry dis-
ables the amplifier output stage. The amplifiers are
enabled once the junction temperature cools by +15°C.
This results in a pulsing output under continuous ther-
mal-overload conditions as the device heats and cools.
Power Supplies
The MAX9789/MAX9790 have separate supply pins for
each portion of the device, allowing for the optimum
combination of headroom and power dissipation and
noise immunity. The speaker amplifiers are powered
from PVDD. PVDD ranges from 4.5V to 5.5V. The head-
phone amplifiers are powered from HPVDD and PVSS.
HPVDD is the positive supply of the headphone ampli-
fiers and ranges from 3V to 5.5V. PVSS is the negative
supply of the headphone amplifiers. Connect PVSS to
CPVSS. The charge pump is powered by CPVDD.
CPVDD ranges from 3V to 5.5V and should be the same
potential as HPVDD. The charge pump inverts the volt-
age at CPVDD, and the resulting voltage appears at
CPVSS. The internal LDO and the remainder of the
device is powered by VDD.
Component Selection
Supply Bypassing
The MAX9789/MAX9790 have separate supply pins for
each portion of the device, allowing for the optimum
combination of headroom and power dissipation and
noise immunity.
Speaker Amplifier Power-Supply Input (PVDD)
The speaker amplifiers are powered from PVDD. PVDD
ranges from 4.5V to 5.5V. Bypass PVDD with a 0.1F
capacitor to PGND. Note additional bulk capacitance is
required at the device if long input traces between
PVDD and the power source are used.
P
V
R
DISS MAX
DD
L
() =
2
π
P
TT
DISSPKG MAX
J MAX
A
JA
()
=
θ
SPKR_OUTL
SPKR_OUTR
SPKR_INL
SPKR_INR
OUTL+
OUTL-
OUTR+
OUTR-
CODEC
CIN1
LINE_OUTR
LINE_OUTL
HP_INL
HP_INR
HPL
HPR
MAX9789
CIN1
CIN2
Figure 6. Mono Signal Output Configuration for MAX9789
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