參數(shù)資料
型號(hào): MAX8632ETI
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs 14-CDIP -55 to 125
中文描述: 集成的DDR電源適用于臺(tái)式機(jī),筆記本電腦解決方案和圖形卡
文件頁(yè)數(shù): 14/29頁(yè)
文件大?。?/td> 512K
代理商: MAX8632ETI
M
remains fixed) and less output voltage ripple. Penalties
for using higher inductor values include larger physical
size and degraded load-transient response, especially
at low input-voltage levels.
DC output accuracy specifications refer to the threshold
of the error comparator. When the inductor is in continu-
ous conduction, the MAX8632 regulates the valley of the
output ripple, so the actual DC output voltage is higher
than the trip level by 50% of the output ripple voltage. In
discontinuous conduction (
SKIP
= GND and I
LOAD
<
I
LOAD(
SKIP
)
), the output voltage has a DC regulation
level higher than the error-comparator threshold by
approximately 1.5% due to slope compensation.
Forced-PWM Mode (
SKIP
= AV
DD
)
The low-noise forced-PWM mode (
SKIP
= AV
DD
) dis-
ables the zero-crossing comparator, which controls the
low-side switch on-time. This forces the low-side gate-
drive waveform to constantly be the complement of the
high-side gate-drive waveform, so the inductor current
reverses at light loads while DH maintains a duty factor
of V
OUT
/ V
IN
. Forced-PWM mode keeps the switching
frequency fairly constant. However, forced-PWM opera-
tion comes at a cost where the no-load V
DD
bias cur-
rent remains between 2mA and 20mA due to the
external MOSFET’s gate charge and switching frequen-
cy. Forced-PWM mode is most useful for reducing
audio frequency noise, improving load-transient
response, and providing sink-current capability for
dynamic output-voltage adjustment.
Current-Limit Buck Regulator (ILIM)
Valley Current Limit
The current-limit circuit for the buck regulator portion of
the MAX8632 employs a unique “valley” current-sensing
algorithm that senses the voltage drop across LX and
PGND1 and uses the on-resistance of the rectifying
MOSFET (Q2 in the Typical Applications Circuit of
Figure 8) as the current-sensing element. If the magni-
tude of the current-sense signal is above the valley cur-
rent-limit threshold, the PWM controller is not allowed to
initiate a new cycle (Figure 4). With valley current-limit
sensing, the actual peak current is greater than the val-
ley current-limit threshold by an amount equal to the
inductor current ripple. Therefore, the exact current-limit
characteristic and maximum load capability are a func-
tion of the current-sense resistance, inductor value, and
input voltage. When combined with the undervoltage-
protection circuit, this current-limit method is effective in
almost every circumstance.
In forced-PWM mode, the MAX8632 also implements a
negative current limit to prevent excessive reverse induc-
tor currents when the buck regulator output is sinking
current. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
tracks the positive current limit when V
ILIM
is adjusted.
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. A 2μA to 20μA divider current is
recommended for accuracy and noise immunity.
The current-limit threshold adjustment range is from
25mV to 200mV. In the adjustable mode, the current-
limit threshold voltage (from PGND1 to LX) is precisely
1/10th the voltage seen at ILIM. The threshold defaults
to 50mV when ILIM is connected to AV
DD
. The logic
threshold for switchover to the 50mV default value is
approximately AV
DD
- 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the differ-
ential current-sense signals seen between LX and GND.
POR, UVLO, and Soft-Start
Internal power-on reset (POR) occurs when AV
DD
rises
above approximately 2V, resetting the fault latch and
the soft-start counter, powering up the reference, and
preparing the buck regulator for operation. Until AV
DD
reaches 4.25V (typ), AV
DD
undervoltage-lockout
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
14
______________________________________________________________________________________
Figure 2. Pulse-Skipping/Discontinuous Crossover Point
I
ON-TIME
0
TIME
I
PEAK
I
LOAD
= I
PEAK
/ 2
I
t
V
IN
- V
OUT
L
=
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