參數(shù)資料
型號(hào)： MAX8632
廠(chǎng)商： Maxim Integrated Products, Inc.
英文描述： Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs 20-LCCC -55 to 125
中文描述： 集成DDR電源方案，適用于臺(tái)式機(jī)、筆記本電腦和圖形卡
文件頁(yè)數(shù)： 16/29頁(yè)
文件大?。?/td> 512K
代理商： MAX8632
M
Power-OK (POK1)
POK1 is an open-drain output for a window comparator
that continuously monitors V
OUT
. POK1 is actively held
low when
SHDN
is low and during the buck regulator
output’s soft-start. After the digital soft-start terminates,
POK1 becomes high impedance as long as the output
voltage is within ±10% of the nominal regulation voltage
set by FB. When V
OUT
drops 10% below or rises 10%
above the nominal regulation voltage, the MAX8632
pulls POK1 low. Any fault condition forces POK1 low
until the fault latch is cleared by toggling
SHDN
or
cycling AV
DD
power below 1V. For logic-level output
voltages, connect an external pullup resistor between
POK1 and AV
DD
. A 100k
resistor works well in most
applications. Note that the POK1 window detector is
completely independent of the overvoltage- and under-
voltage-protection fault detectors and the state of VTTS
and VTTR.
SHDN
and Output Discharge
The
SHDN
input corresponds to the buck regulator and
places the buck regulator’s portion of the IC in a low-
power mode (see the
Electrical Characteristics
table).
SHDN
is also used to reset a fault signal such as an
overvoltage or undervoltage fault.
When output discharge is enabled, (OVP/UVP = AV
DD
or open) and
SHDN
is pulled low, or if UVP is enabled
(OVP/UVP = AV
DD
) and V
OUT
falls to 70% of its regula-
tion set point, the MAX8632 discharges the buck regu-
lator output (through the OUT input) through an internal
10
switch to ground. While the output is discharging,
DL is forced low and the PWM controller is disabled but
the reference remains active to provide an accurate
threshold. Once the output voltage drops below 0.1V,
the MAX8632 shuts down the reference and DL
remains low.
When output discharge is disabled (OVP/UVP = REF or
GND), the controller does not actively discharge the
buck output and the DL driver remains low. Under these
conditions, the buck output discharge rate is determined
by the load current and its output capacitance. The buck
regulator detects and latches the discharge-mode state
set by the OVP/UVP setting on startup.
When OUT is discharging, both VTT and VTTR outputs
remain alive and continue to track REFIN until OUT
drops to 0.1V.
STBY
The
STBY
input is an active-low input that is used to
shut down only the VTT output. When
STBY
is low, VTT
is high impedance.
Power-OK (POK2)
POK2 is the open-drain output for a window compara-
tor that continuously monitors the VTTS input and VTTR
output. POK2 is pulled low when REFIN is less than
0.8V. POK2 is high impedance as long as the output
voltage is within ±10% of the nominal regulation voltage
as set by REFIN. When V
VTTS
or V
VTTR
rises 10%
above or 10% below its nominal regulation voltage, the
MAX8632 pulls POK2 low. For logic-level output volt-
ages, connect an external pullup resistor between
POK2 and AV
DD
. A 100k
resistor works well in most
applications.
Current Limit (LDO for VTT
and VTTR Buffer)
The VTT output is a linear regulator that regulates the
input (VTTI) to half the V
REFIN
voltage. The feedback
point for VTT is at the VTTS input (Figure 1). VTT is
capable of sinking and sourcing at least 1.5A of continu-
ous current and 3A peak current. The current limit for
VTT and VTTR is typically ±5A and ±32mA, respective-
ly. When the current limit for either output is reached,
the outputs regulate the current, not the voltage.
Fault Protection
The MAX8632 provides overvoltage/undervoltage fault
protection in the buck controller. Select OVP/UVP to
enable and disable fault protection as shown in Table 3.
Once activated, the controller continuously monitors the
output for undervoltage and overvoltage fault conditions.
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
16
______________________________________________________________________________________
Table 2. Shutdown and Standby Control Logic
SHDN
AV
DD
*
AV
DD
**
GND***
STBY
AV
DD
*
GND**
X
BUCK OUTPUT (V
DDQ
)
ON
ON
OFF
VTT
ON
VTTR
ON
ON
OFF (high impedance)
OFF (tracking 0.5 REFIN)
OFF (tracking 0.5 REFIN)
*
For DDR application, this is referred as S0 state, where all outputs are on.
**
For DDR application, this is referred as S3 state, where V
DDQ
and VTTR are kept on, but VTT is turned off (high impedance).
***
For DDR application, this is referred as S4/S5 states, where all outputs are off. Discharge mode should be selected (OVP/UVP =
AV
DD
or OPEN, see Table 3) to discharge the outputs.
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