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參數(shù)資料
| 型號： | MAX5945CAX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | Quad Network Power Controller for Power-Over-LAN |
| 中文描述： | 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO36 |
| 封裝： | 0.80 MM PICTH, SSOP-36 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大小： | 572K |
| 代理商： | MAX5945CAX |
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M
Message Format for Reading
The MAX5945 reads using the MAX5945’s internally
stored command byte as an address pointer, the same
way the stored command byte is used as an address
pointer for a write. The pointer auto-increments after
reading each data byte using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX5945’s command byte by performing a write
(Figure 12). The master now reads ‘n’ consecutive
bytes from the MAX5945, with the first data byte read
from the register addressed by the initialized command
byte (Figure 13). When performing read-after-write veri-
fication, remember to reset the command byte’s
address because the stored control byte address auto-
increments after the write.
Operation with Multiple Masters
When the MAX5945 operates on a 2-wire interface with
multiple masters, a master reading the MAX5945
should use repeated starts between the write that sets
the MAX5945’s address pointer, and the read(s) that
takes the data from the location(s). It is possible for
master 2 to take over the bus after master 1 has set up
the MAX5945’s address pointer but before master 1
has read the data. If master 2 subsequently resets the
MAX5945’s address pointer then master 1’s read may
be from an unexpected location.
Command Address Auto-Incrementing
Address auto-incrementing allows the MAX5945 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX5945
generally increments after each data byte is written or
read (Table 4). The MAX5945 is designed to prevent
overwrites on unavailable register addresses and unin-
tentional wrap-around of addresses.
Register Map And Description
The interrupt register (Table 5) summarizes the event
register status and is used to send an interrupt signal
(
INT
goes low) to the controller. Writing a 1 to R1Ah[7]
clears all interrupt and events registers. A reset sets
R00h to 00h.
INT_EN (R17h[7]) is a global interrupt mask (Table 6).
The MASK_ bits activate the corresponding interrupt
bits in register R00h. Writing a 0 to INT_EN (R17h[7])
disables the
INT
output.
A reset sets R01h to AAA00A00b, where A is the state
of the AUTO input prior to the reset.
The power event register (Table 7) records changes in
the power status of the four ports. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change
in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1.
PG_CHG_ and PWEN_CHG_ trigger on the edges of
PGOOD_ and PWR_EN_ and do not depend on the
actual level of the bits. The power event register has
two addresses. When read through the R02h address,
the content of the register is left unchanged. When read
through the CoR R03h address, the register content will
be cleared. A reset sets R02h/R03h = 00h.
DET_END_/CL_END_ is set high whenever detection/
classification is completed on the corresponding port.
A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1
in any of the DET_END_ bits forces R00h[3] to 1. As
with any other events register, the detect event register
(Table 8) has two addresses. When read through the
R04h address, the content of the register is left
unchanged. When read through the CoR R05h
address, the register content will be cleared. A reset
sets R04h/R05h = 00h.
LD_DISC_ is set high whenever the corresponding port
shuts down due to detection of load removal.
IMAX_FLT_ is set high when the port shuts down due to
an extended overcurrent event after a successful start-
up. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1.
A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1.
As with any of the other events register, the fault event
register (Table 9) has two addresses. When read
through the R06h address, the content of the register is
left unchanged. When read through the CoR R07h
address, the register content will be cleared. A reset
sets R06h/R07h = 00h.
Quad Network Power Controller
for Power-Over-LAN
22
______________________________________________________________________________________
COMMAND BYTE
ADDRESS RANGE
AUTO-INCREMENT BEHAVIOR
0x00 to 0x26
Command address will auto-
increment after byte read or written
0x26
Command address remains at 0x26
after byte written or read
Table 4. Auto-Increment Rules
相關PDF資料 |
PDF描述 |
|---|---|
| MAX5945EAX | Quad Network Power Controller for Power-Over-LAN |
| MAX5948 | AND-OR-invert Gates 14-CFP -55 to 125 |
| MAX5948A | -48V Hot-Swap Controllers with External RSENSE |
| MAX5948AESA | -48V Hot-Swap Controllers with External RSENSE |
| MAX5948B | 4-2-3-2 Input AND-OR-invert Gates 14-CDIP -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5945CAX+ | 功能描述:熱插拔功率分布 IEEE 802.3af Quad Net Pwr Controller RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5945CAX+T | 功能描述:熱插拔功率分布 IEEE 802.3af Quad Net Pwr Controller RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5945CAX-T | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5945EAX | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5945EAX+ | 功能描述:熱插拔功率分布 IEEE 802.3af Quad Net Pwr Controller RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
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