參數(shù)資料
型號(hào): MAX5922AEUI+
廠商: Maxim Integrated
文件頁(yè)數(shù): 10/21頁(yè)
文件大?。?/td> 437K
描述: IC NETWORK PWR SW +48V 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
類(lèi)型: 以太網(wǎng)供電開(kāi)關(guān)(PoE)
應(yīng)用: 遠(yuǎn)程外設(shè)(工業(yè)控制,相機(jī),數(shù)據(jù)訪問(wèn))
內(nèi)部開(kāi)關(guān):
電源電壓: 32 V ~ 60 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1411 (CN2011-ZH PDF)
+48V, Single-Port Network Power Switch
For Power-Over-LAN
10   ______________________________________________________________________________________
PIN
NAME
FUNCTION
*
AGND
Analog Ground. This is the return of analog power input. AGND can vary ?V from DGND. AGND and
DGND must be connected together at a single point in the system.
1, 2
DRAIN
Drain connection for the integrated MOSFET. Connect a sense resistor, R
SENSE
, from DRAIN to IN.
These pins are also the current-sense resistor negative terminal. R
SENSE
 sets the overcurrent-limit
and open-circuit detection threshold. These two pins must be connected together.
3, 6, 26
N.C.
No Connection. Not internally connected. Leave pins 6 and 26 open. Pins 6 and 26 are left
unconnected to provide additional spacing between the high-voltage pins and other pins.
4
IN
Input Voltage. Connect to a positive voltage source between +32V to +60V from IN to AGND. This is
the current-sense resistor positive terminal. Bypass to AGND with a 47礔, 100V electrolytic capacitor
and a 0.1礔, 100V ceramic capacitor. Place the ceramic capacitor close to this pin.
5
RCL
Classification Sense Resistor. Connect a 150& ?% resistor from RCL to IN for sensing the
classification current. Leave RCL floating when the PD classification function is not used.
7
AGND_S
Analog Ground Sense. Connect a 1& resistor from AGND_S to AGND. This resistor protects the IC
during an output short-circuit condition.
8
UVLO
Undervoltage Lockout Adjustment Input. Referenced to AGND. Connect to the center point of a
resistive-divider from IN to AGND to adjust the UVLO threshold. Leave open for default value.
9
RDT
Detection Sense Resistor. Connect an 18.2k& ?% resistor from RDT to AGND for sensing the PD
detection current. Add a 680nF capacitor in parallel to this resistor to filter out the power-line noise.
Connect RDT to AGND when the PD detection function is not used.
10
FAULT
Fault Signal Open-Drain Logic Output. Reference to DGND. FAULT is latched low when:
1.  An overtemperature condition occurs and/or,
2.  An overcurrent condition that has lasted for more than t
OC
.
11
POK
Power-OK, Open-Drain Logic Output. Reference to DGND. POK goes open drain a time t
POK_HIGH
after V
OUT
 raises to within V
THPOK
 from V
IN
. POK goes low a time t
POK_LOW
 after V
OUT
 falls out of the
V
THPOK
from V
IN
.
12
ZC
Zero-Current Fault Signal. Open-drain logic output. Reference to DGND. ZC is latched low when there
is a zero-current condition lasting longer than t
ZCDEL
. ZC is open-drain otherwise. The zero-current
detection circuit is enabled immediately after the POK signal goes high. The ZC is unlatched after a
valid PD has been detected and eventually classified.
13
TP1
Must be Left Open or Connected to AGND
14
TP2
Must be Left Open or Connected to AGND
15
TP3
Must be Left Open or Connected to AGND
16
CL2
Classification Report Logic Output Bit 2. See the PD Classification section (Table 2).
17
CL1
Classification Report Logic Output Bit 1. See the PD Classification section (Table 2).
18
CL0
Classification Report Logic Output Bit 0. See the PD Classification section (Table 2).
19
DGND
Digital Ground. DGND can vary ?V from AGND. DGND and AGND must to be connected together at
a single point in the system.
20
LATCH
Fault Management Selection Digital Input. Referenced to DGND. Connect to a logic high to latch off
after a fault condition. Connect to a logic low for automatic restart after a fault condition (see the Fault
Management section).
Pin Description
*This is not a device pin.
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