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參數(shù)資料
| 型號： | MAX5887 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs |
| 中文描述： | 3.3V、14位、500Msps、高動態(tài)性能DAC，差分LVDS輸入 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 982K |
| 代理商： | MAX5887 |
M
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
10
______________________________________________________________________________________
plane, IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5887.
Clock Inputs (CLKP, CLKN)
The MAX5887 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the lowest possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For sin-
gle-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1μF capacitor.
The CLKP and CLKN pins are internally biased to 1.5V.
This allows the user to AC-couple clock sources directly
to the device without external resistors to define the DC
level. The input resistance of CLKP and CLKN is >5k
.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from an
LVDS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled ECL drive for
best performance.
Data Timing Relationship
Figure 5 shows the timing relationship between differ-
ential, digital LVDS data, clock, and output signals. The
MAX5887 features a 1.8ns hold, a -0.8ns setup, and a
1.8ns propagation delay time. There is a four-clock-
cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
LVDS-Compatible Digital Inputs
(B0P–B13P, B0N–B13N)
The MAX5887 features LVDS receivers on the bus input
interface. These LVDS inputs (B0P/N through B13P/N)
allow for a low-differential voltage swing with low con-
stant power consumption across a large range of
0.1
μ
F
1.2V
REFERENCE
10k
I
REF
R
SET
DACREF
FSADJ
REFIO
I
REF
= V
REFIO
/R
SET
CURRENT-STEERING
DAC
AV
DD
IOUTP
IOUTN
Figure 2. Reference Architecture, Internal Reference
Configuration
I
OUT
I
OUT
IOUTN
IOUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AV
DD
Figure 3. Simplified Analog Output Structure
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
1:1
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
TO
DAC
CLKP
0.1
μ
F
0.1
μ
F
CLKN
CLKGND
25
25
Figure 4. Differential Clock Signal Generation
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAX5887EGK | 制造商:Maxim Integrated Products 功能描述:3.3V, 14-BIT, 500MBPS HIGH DYNAMIC PERFORMAN - Rail/Tube |
| MAX5887EGK/GG8 | 制造商:Maxim Integrated Products 功能描述:3.3V, 14-BIT, 500MBPS HIGH DYNAMIC PERFORMAN - Rail/Tube |
| MAX5887EGK+D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14-Bit 500Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5887EGK+TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14-Bit 500Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5887EGK-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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