參數(shù)資料
型號(hào)： MAX5866ETM+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 4/26頁(yè)
文件大小： 0K
描述： IC ANLG FRONT END 60MSPS 48-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 4
功率（瓦特）： 2.10W
電壓 - 電源，模擬： 2.7 V ~ 3.3 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.3 V
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
12
______________________________________________________________________________________
PIN
NAME
FUNCTION
1
REFP
Upper Reference Voltage. Bypass with a 0.33F capacitor to GND as close to REFP as possible.
2, 8, 11,
33, 39, 43
VDD
Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with a
0.1F capacitor.
3
IA+
Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+.
4
IA-
Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM.
5, 7, 12, 37,
42
GND
Analog Ground. Connect all pins to GND ground plane.
6
CLK
Conversion Clock Input. Clock signal for both ADCs and DACs.
9
QA-
Channel QA Negative Analog Input. For single-ended operation, connect QA- to COM.
10
QA+
Channel QA Positive Analog Input. For single-ended operation, connect signal source to QA+.
13–16, 19–22
DA0–DA7
ADC Tri-State Digital Output Bits. DA7 is the most significant bit (MSB), and DA0 is the least
significant bit (LSB).
17
OGND
Output Driver Ground
18
OVDD
Output Driver Power Supply. Supply range from +2.7V to VDD to accommodate most logic levels.
Bypass OVDD to OGND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor.
23–32
DD0–DD9
DAC Digital Input Bits. DD9 is the MSB, and DD0 is the LSB.
34
DIN
3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK.
35
SCLK
3-Wire Serial-Interface Clock Input
36
CS
3-Wire Serial-Interface Chip-Select Input. Apply logic low to enable the serial interface.
38
N.C.
No Connection
40, 41
QD+, QD-
DAC Channel-QD Differential Voltage Output
44, 45
ID-, ID+
DAC Channel-ID Differential Voltage Output
46
REFIN
Reference Input. Connect to VDD for internal reference.
47
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33F capacitor.
48
REFN
Negative Reference I/O. Conversion range is
±(VREFP - VREFN). Bypass REFN to GND with a 0.33F
capacitor.
—EP
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
Pin Description
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