參數(shù)資料
型號： MAX5852ETL
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： Quadruple 2-Input Exclusive-OR Gates 14-CFP -55 to 125
中文描述： DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.012 us SETTLING TIME, 8-BIT DAC, QCC40
封裝： 6 X 6 MM, 0.8 MM HEIGHT, MO-220-WJJD-2, TQFN-40
文件頁數(shù)： 4/18頁
文件大?。?/td> 1290K
代理商： MAX5852ETL
M
Dual, 8-Bit, 165Msps, Current-Output DAC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= CV
DD
= 3V, AGND = DGND = CGND = 0, f
DAC
= 165Msps, differential clock, external reference, V
REF
= 1.2V,
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by
production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal-Reference Supply
Rejection
AV
DD
varied from 2.7V to 3.6V
0.5
mV/V
Internal-Reference Output-
Voltage Temperature Drift
TCV
REFO
REN
= 0
±50
ppm/°C
Internal-Reference Output Drive
Capability
REN
= 0
50
μA
External-Reference Input Voltage
Range
REN
= 1
0.10
1.2
1.32
V
Current Gain
LOGIC INPUTS
(DA7–DA0, DB7–DB0,
CW
)
I
FS
/I
REF
32
mA/mA
Digital Input-Voltage High
V
IH
0.65 x
DV
DD
V
Digital Input-Voltage Low
V
IL
0.3 x
DV
DD
+1
V
Digital Input Current
Digital Input Capacitance
SINGLE-ENDED CLOCK INPUT/OUTPUT AND
DCE
INPUT
(CLK,
DCE
)
I
IN
C
IN
-1
μA
pF
3
Digital Input-Voltage High
V
IH
DCE
= 1
0.65 x
CV
DD
V
Digital Input-Voltage Low
V
IL
DCE
= 1
0.3 x
CV
DD
+1
V
Digital Input Current
Digital Input Capacitance
I
IN
C
IN
DCE
= 1
DCE
= 1
-1
μA
pF
3
Digital Output-Voltage High
V
OH
DCE
= 0, I
SOURCE
= 0.5mA, Figure 1
0.9 x
CV
DD
V
Digital Output-Voltage Low
V
OL
DCE
= 0, I
SINK
= 0.5mA, Figure 1
0.1 x
CV
DD
V
DIFFERENTIAL CLOCK INPUTS
(CLKXP/CLKXN)
Differential Clock Input Internal
Bias
CV
DD
/2
V
Differential Clock Input Swing
Clock Input Impedance
POWER REQUIREMENTS
Analog Power-Supply Voltage
Digital Power-Supply Voltage
Clock Power-Supply Voltage
0.5
V
Measured single ended
5
k
AV
DD
DV
DD
CV
DD
2.7
2.7
2.7
3
3
3
3.6
3.6
3.6
V
V
V
相關(guān)PDF資料
PDF描述
MAX5858 Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125
MAX5858ECM Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
MAX5863 Quadruple Differential Line Receiver 16-CDIP -55 to 125
MAX5863ETM 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
MAX5864 Quadruple Differential Line Receiver 16-CDIP -55 to 125
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX5852ETL+ 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 2Ch 165Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5852ETL+T 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 2Ch 165Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5852ETL-T 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5852EVKIT 功能描述:數(shù)模轉(zhuǎn)換器- DAC Evaluation Kit for the MAX5851 MAX5852 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5853ETL 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*