參數(shù)資料
型號(hào): MAX5852ETL
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Quadruple 2-Input Exclusive-OR Gates 14-CFP -55 to 125
中文描述: DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.012 us SETTLING TIME, 8-BIT DAC, QCC40
封裝: 6 X 6 MM, 0.8 MM HEIGHT, MO-220-WJJD-2, TQFN-40
文件頁(yè)數(shù): 17/18頁(yè)
文件大?。?/td> 1290K
代理商: MAX5852ETL
M
Dual, 8-Bit, 165Msps, Current-Output DAC
______________________________________________________________________________________
17
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either out-
put tone to the worst 3rd-order (or higher) IMD products.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. For a DAC,
the deviations are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A
DNL error specification no more negative than -1 LSB
guarantees monotonic transfer function.
Offset Error
Offset error is the current flowing from positive DAC
output when the digital input code is set to zero. Offset
error is expressed in LSBs.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step. The ideal current is
defined by reference voltage at 32 x V
REFO
/ R
SET
.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value to within the converter’s specified
accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011…111 to 100…000. This occurs due
to timing variations between the bits. The glitch impulse
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch impulse is usu-
ally specified in pV-s.
PART
SPEED (Msps)
RESOLUTION
MAX5851
MAX5852
MAX5853
MAX5854
80
165
80
165
8 bit, dual
8 bit, dual
10 bit, dual
10 bit, dual
Table 4. Part Selection Table
Chip Information
TRANSISTOR COUNT: 9035
PROCESS: CMOS
相關(guān)PDF資料
PDF描述
MAX5858 Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125
MAX5858ECM Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
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