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參數(shù)資料
| 型號： | MAX5852ETL |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | Quadruple 2-Input Exclusive-OR Gates 14-CFP -55 to 125 |
| 中文描述： | DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.012 us SETTLING TIME, 8-BIT DAC, QCC40 |
| 封裝： | 6 X 6 MM, 0.8 MM HEIGHT, MO-220-WJJD-2, TQFN-40 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 1290K |
| 代理商： | MAX5852ETL |
M
Dual, 8-Bit, 165Msps, Current-Output DAC
12
______________________________________________________________________________________
Device Power-Up and
States of Operation
At power-up, the MAX5852’s default configuration is
internal reference, noninterleaved input mode with a gain
of 0dB and a fully operational converter. In shutdown,
the MAX5852 consumes only 1μA of supply current, and
in standby the current consumption is 3.1mA. Wake-up
time from standby mode to normal operation is 3μs.
Clock Modes
The MAX5852 allows both single-ended CMOS and dif-
ferential clock mode operation, and supports update
rates of up to 165Msps. These modes are selected
through an active-low control line called
DCE
. In single-
ended clock mode (
DCE
= 1), the CLK pin functions as
an input, which accepts a user-provided single-ended
clock signal. Data is written to the converter on the rising
edge of the clock. The DAC outputs (previous data) are
updated simultaneously on the same edge.
If the
DCE
pin is pulled low, the MAX5852 will operate in
differential clock mode. In this mode, the clock signal has
to be applied to differential clock input pins
CLKXP/CLKXN. The differential input accepts an input
range of
≥
0.5V
P-P
and a common-mode range of 1V to
(CV
DD
- 0.5V), making the part ideal for low- input ampli-
tude clock drives. CLKXP/CLKXN also help to minimize
the jitter, and allow the user to connect a crystal oscillator
directly to MAX5852.
CONTROL WORD
PD
DACEN
FUNCTION
Power-Down. The part enters power-down mode if PD = 1.
DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
IDE
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both
channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge
of the clock signal and channel A data is written on the rising edge of the clock signal.
REN
Reference Enable Bit.
REN
= 0 activates the internal reference.
REN
= 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
G3
G2
G1
G0
Bit 3 (MSB) of Gain Adjust Word
Bit 2 of Gain Adjust Word
Bit 1 of Gain Adjust Word
Bit 0 (LSB) of Gain Adjust Word
Table 1. Control Word Format and Function
MODE
PD
DACEN
IDE
REN
Normal operation;
noninterleaved inputs;
internal reference active
0
1
0
0
Normal operation;
noninterleaved inputs;
internal reference disabled
0
1
0
1
Normal operation;
interleaved inputs; internal
reference disabled
0
1
1
1
Standby
Power-down
Power-up
0
1
0
0
X
1
X
X
X
X
X
X
Table 2. Configuration Modes
GAIN ADJUSTMENT ON
CHANNEL A (dB)
G3
G2
G1
G0
+0.4
0
-0.35
0
1
1
0
0
1
0
0
1
0
0
1
Table 3. Gain Difference Setting
X = Don’t care.
MSB LSB
PD
DACEN
IDE
REN
G3
G2
G1
G0
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