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參數(shù)資料
| 型號： | MAX550BC |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Power, +2.5V to +5.5V, 8-Bit Voltage-Output DAC in レMAX |
| 中文描述： | 低功耗，2.5V至5.5V，8位電壓輸出DAC最大的レ |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 112K |
| 代理商： | MAX550BC |
M
Low-Power, +2.5V to +5.5V, 8-Bit
Voltage-Output DAC in μMAX
8
_______________________________________________________________________________________
Table 1. Control-Byte/Input-Word Bit
Definitions
UB1*
X
UB2
X
UB3
X
C2
0
C2
1
X = Don’t care
*Clocked in first
**Clocked in last
Unassigned Bit 1
Unassigned Bit 2
Unassigned Bit 3
Power-Up Mode
Power-Down Mode
C1
0
DAC Register Load Operation
Disabled
C1
1
DAC Register Load Operation
Enabled
C0
0
DAC Output Updated on Rising
Edge of
CS
C0
AB1
AB2
D7
D6
D5
D4
D3
D2
D1
D0**
1
0
1
X
X
X
X
X
X
X
X
Unassigned Operation
Assigned Bit 1
Assigned Bit 2
DAC Data Bit 7 (MSB)
DAC Data Bit 6
DAC Data Bit 5
DAC Data Bit 4
DAC Data Bit 3
DAC Data Bit 2
DAC Data Bit 1
DAC Data Bit 0 (LSB)
Data
Byte
Microprocessor Interfacing
The MAX550B serial interface is compatible with
Microwire, SPI, and QSPI interface standards. For SPI,
clear the CPOL and CPHA bits (CPOL = 0 and
CPHA = 0). CPOL = 0 sets the idle clock state to zero
and CPHA = 0 changes data at SCLK’s falling edge.
This setting allows SPI to run at full clock speeds
(1.5MHz). If a serial port is not available on your μP,
three bits of a parallel port can be used to emulate a
serial port by bit manipulation. Minimize digital
feedthrough at the DAC output by operating the serial
clock only when necessary.
––––––––––––––
Applic ations Information
Power-S upply
and Ground Considerations
Connect GND to the highest-quality ground available.
Bypass V
DD
with a 0.1μF to 0.22μF capacitor to GND.
The reference input can be used without bypassing.
However, for optimum line/load-transient response and
noise performance, bypass the reference input with a
0.1μF to 4.7μF capacitor to GND.
Careful PC board layout minimizes crosstalk between
the DAC output, the reference, and the digital inputs.
Separate analog traces by running ground traces
between them. Make sure high-frequency digital lines
are not routed parallel to analog lines.
CS
SCLK
DIN
t
DS
t
DH
t
CL
t
CH
t
CSS0
t
CSH0
t
CSW
t
CSH1
t
CSS1
Figure 3. Detailed Serial-Interface Timing Diagram
Control
Byte
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