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參數(shù)資料
| 型號： | MAX550BC |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Power, +2.5V to +5.5V, 8-Bit Voltage-Output DAC in レMAX |
| 中文描述： | 低功耗，2.5V至5.5V，8位電壓輸出DAC最大的レ |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 112K |
| 代理商： | MAX550BC |
Low-Power, +2.5V to +5.5V, 8-Bit
Voltage-Output DAC in μMAX
_______________________________________________________________________________________
7
M
DIN
SCLK
CS
UB1 UB2 UB3 C2
C1
C0
AB1 AB2
D7
D6
D5
D4
D3
D2
D1
D0
OPTIONAL
PAUSE
INSTRUCTION
EXECUTED
Figure 2. Serial-Interface Timing Diagram
DAC Output
The MAX550B’s output is unbuffered; it connects
directly to the R-2R ladder. This configuration minimizes
power consumption and reduces offset errors. For high-
est accuracy, apply high resistive loads (1M
and up).
Lower resistive loads can be driven, but output loading
increases full-scale error. The magnitude of the expect-
ed error is the ratio of the DAC output resistance to the
DC load resistance at the output.
Typically, an energy pulse is coupled into the DAC output
on the rising edge of
CS
. Since the MAX550B’s output is
unbuffered (connected directly to the R-2R ladder), con-
necting a small capacitor (200pF to 1000pF) from the out-
put to ground creates a lowpass filter that effectively
suppresses the pulse for sensitive applications (see
Output Glitch Filtering graph in the Typical Operating
Characteristics).
Shutdown Mode
When the MAX550B is in shutdown mode, REF becomes
high impedance. The supply current is unchanged, but
the REF input current decreases to less than 1μA. This
allows the system reference to remain active with minimal
power consumption.
When exiting shutdown mode, the output recovery time
is equivalent to the DAC settling time.
S erial Interfac e
The MAX550B interface is compatible with 3-wire SPI,
QSPI, and Microwire microprocessor (μP) interface
standards. An active-low chip select (
CS
) enables the
input shift register to receive data from the serial input,
DIN (Figure 2). Data is clocked into the input shift register
on rising edges of the serial clock signal (SCLK). The
clock frequency can be as high as 10MHz.
When writing to the DAC, transmit data MSB first in
one 16-bit word or two 8-bit bytes. The write cycle can
be segmented when
CS
is kept active (low) to allow
two 8-bit-wide transfers. After clocking all 16 bits into
the input shift register, a rising edge on
CS
programs
the DAC. The DAC output reflects the data stored in the
DAC register. Figure 3 gives detailed timing infor-
mation.
Initialization
The MAX550B has an internal power-on reset. At
power-up, all internal registers are reset to zero; there-
fore, an initialization write is not necessary.
Serial Input Data Format and Control Codes
The control byte programs the DAC (Table 1). Table 2
lists the MAX550B’s serial-input command format. The
16-bit input word consists of an 8-bit control byte and
an 8-bit data byte. The 8-bit control byte is not decoded
internally; every control bit performs one function. Data
is clocked in starting with unassigned bit 1 (UB1), fol-
lowed by the remaining control bits and the DAC data
byte. The LSB (D0) of the data byte is the last bit
clocked into the input shift register (Figure 2).
Table 3 is an example of a 16-bit word. It performs the
following functions:
1) Load 80 hex (128 decimal) into the DAC register.
2) Update the DAC output on
CS
’s rising edge.
Table 4 shows how to calculate the output voltage
based on the input code.
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