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參數(shù)資料
| 型號： | MAX550BC |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Power, +2.5V to +5.5V, 8-Bit Voltage-Output DAC in レMAX |
| 中文描述： | 低功耗，2.5V至5.5V，8位電壓輸出DAC最大的レ |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 112K |
| 代理商： | MAX550BC |
M
Low-Power, +2.5V to +5.5V, 8-Bit
Voltage-Output DAC in μMAX
_______________________________________________________________________________________
3
TIMING CHARACTERISTICS (Note 5)
(V
DD1 =
V
DD2
= +2.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Digital inputs switching from 0V to V
DD_.
)
ELECTRICAL CHARACTERISTICS (continued)
(V
DD1 =
V
DD2
= +2.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
CS
= high, all digital inputs from 0V to V
DD_
V
DD_
= 5.5V, output unloaded,
all inputs = GND or V
DD_
Output unloaded, all inputs = GND or V
DD
To ±1/2LSB, C
L
= 20pF
C
LOAD
= 20pF
Shutdown mode
CONDITIONS
μA
0.3
Shutdown Current
nV-sec
50
Digital Feedthrough and
Crosstalk
μA
0.3
10
I
DD1 +
I
DD2
Supply Current
V
2.5
5.5
V
DD_
Supply Voltage Range
μs
4
Voltage-Output Settling Time
V/μs
1.4
3.1
Voltage-Output Slew Rate
μs
4
Wake-Up Time
POWER SUPPLIES
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
μs
5
V
DD_
High to
CS
Low
ns
30
0
10
t
DS
DIN to SCLK High Setup
ns
40
t
CL
ns
40
t
CH
SCLK Pulse Width High
SCLK Pulse Width Low
ns
80
t
CP
SCLK Period
ns
40
t
CSW
CS
Pulse Width High
10
20
DIN to SCLK High Hold
ns
ns
ns
30
30
20
t
CSS0
t
CSS1
t
CSH0
CS
Low to SCLK High Setup
CS
High to SCLK High Setup
SCLK High to
CS
Low Hold
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Note 1:
0°C to -40°C testing guaranteed by design using six sigma design limits.
Note 2:
Worst-case input resistance at REF occurs at DAC code 55 hex.
Note 3:
Worst-case reference input current occurs at DAC code 55 hex.
Note 4:
Guaranteed by design. Not production tested.
Note 5:
Guaranteed by design. Not production tested.
Power-on reset delay
V
DD_
= 2.5V
V
DD_
= 5.5V
V
DD_
= 2.5V
V
DD_
= 5.5V
C
L
= 20pF
SR
DYNAMIC PERFORMANCE
V
DD_
= 2.5V
V
DD_
= 5.5V
ns
t
DH
ns
t
CSH1
Delay, SCLK High to
CS
High
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