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參數(shù)資料
| 型號(hào)： | MAX518 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs(單通道,串行,電壓輸出,8位D/A轉(zhuǎn)換器) |
| 中文描述： | 2線接口、串行、8位DAC，滿擺幅輸出 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | MAX518 |
M
2-Wire S erial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________
9
these devices may share the bus. The MAX519 has 16
possible slave addresses. The eighth bit (LSB) in the
slave address byte should be low when writing to the
MAX517/MAX518/MAX519.
The MAX517/MAX518/MAX519 monitor the bus continu-
ously, waiting for a START condition followed by their
slave address. When a device recognizes its slave
address, it is ready to accept data.
The Command Byte and Output Byte
A command byte follows the slave address. Figure 7
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
bits except PD (power-down) and RST (reset) are
ignored. If an output byte follows the command byte,
A0 of the command byte indicates the digital address
of the DAC whose input data latch receives the digital
output data. Set this bit to 0 when writing to the
MAX517. The data is transferred to the DAC’s output
latch during the STOP condition following the transmis-
sion. This allows both DACs of the MAX518/MAX519 to
be updated simultaneously (Figure 8).
Setting the PD bit high powers down the MAX517/
MAX518/MAX519 following a STOP condition (Figure
9a). If a command byte with PD set high is followed by
an output byte, the addressed DAC’s input latch will be
updated and the data will be transferred to the DAC’s
output latch following the STOP condition (Figure 9b).
SCL
SDA
0
0
1 or
AD3
1 or
AD2
1
0
AD1
AD0
LSB
ACK
SLAVE ADDRESS
Figure 6. Address Byte
SLAVE ADDRESS BITS AD0, AD1, AD2, AND AD3 CORRESPOND TOTHE LOGIC
STATE OF THE ADDRESS INPUT PINS.
LSB
MSB
SDA
SCL
R2
R1
R0
RST
PD
X
X
A0/0
ACK
Figure 7. Command Byte
R2, R1, R0: RESERVED BITS. SET TO0.
RST: RESET BIT, SET TO1 TORESET ALL DAC REGISTERS.
PD: POWER-DOWN BIT. SET TO1 TOPLACE THE DEVICE IN THE 4μA SHUTDOWN
MODE. SET TO0 TORETURN TOTHE NORMAL OPERATIONAL STATE.
A0: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS
OF DATA IN THE NEXT BYTE. SET TO0 FOR MAX517.
ACK: ACKNOWLEDGE BIT. THE MAX517/MAX518/MAX519 PULLS SDA LOW DURING
THE 9TH CLOCK PULSE.
X: DONT CARE.
START CONDITION
STOP CONDITION
OUTPUT BYTE
COMMAND BYTE
SLAVE ADDRESS BYTE
SCL
SDA
MSB
MSB
MSB
LSB
LSB
LSB
ACK
ACK
ACK
Figure 4. A Complete Serial Transmission
SCL
SDA
START CONDITION
STOP CONDITION
Figure 5. All communications begin with a START condition and
end with a STOP condition, both generated by a bus master.
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