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參數(shù)資料
| 型號(hào)： | MAX518 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs(單通道,串行,電壓輸出,8位D/A轉(zhuǎn)換器) |
| 中文描述： | 2線接口、串行、8位DAC，滿擺幅輸出 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | MAX518 |
M
2-Wire S erial 8-Bit DACs with
Rail-to-Rail Outputs
8
_______________________________________________________________________________________
The address byte and pairs of command and output
bytes are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low, with the exception of START and STOP condi-
tions. SDA’s state is sampled, and therefore must remain
stable while SCL is high. Data is transmitted in 8-bit
bytes. Nine clock cycles are required to transfer the data
bits to the MAX517/MAX518/MAX519. Set SDA low dur-
ing the 9th clock cycle as the MAX517/MAX518/MAX519
pull SDA low during this time. R
C
(see Figure 3) limits the
current that flows during this time if SDA stays high for
short periods of time.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high (Figure 5). When the mas-
ter has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
The Slave Address
The MAX517/MAX518/MAX519 each have a 7-bit long
slave address (Figure 6). The first three bits (MSBs) of
the slave address have been factory programmed and
are always 010. In addition, the MAX517 and MAX518
have the next two bits factory programmed to 1s. The
logic state of the address inputs (AD0 and AD1 on the
MAX517/MAX518; AD0, AD1, AD2, and AD3 on the
MAX519) determine the LSB bits of the 7-bit slave
address. These input pins may be connected to VDD or
DGND, or they may be actively driven by TTL or CMOS
logic levels. The MAX517/MAX518 have four possible
slave addresses and therefore a maximum of four of
MAX518
SDA
SCL
μ
C
SDA
AD0
SCL
+5V
AD1
DUAL
DAC
MAX519
AD0
AD1
SDA
REF1
REF0
R
C
1k
SCL
+4V
+1V
AD2
AD3
DUAL
DAC
SDA
AD0
SCL
AD1
SINGLE
DAC
MAX517
OUT0
OFFSET ADJUSTMENT
OUT1
GAIN ADJUSTMENT
OUT0
BRIGHTNESS ADJUSTMENT
OUT1
CONTRAST ADJUSTMENT
REF0
+2.5V
OUT0
THRESHOLD ADJUSTMENT
Figure 3. MAX517/MAX518/MAX519 Application Circuit
SCL
SDA
t
LOW
t
HIGH
t
F
t
R
t
HD
,
STA
t
HD
,
DAT
t
HD
,
STA
t
SU
,
DAT
t
SU
,
STA
t
BUF
t
SU
,
STO
START CONDITION
STOP CONDITION
REPEATED START CONDITION
START CONDITION
Figure 2. Two-Wire Serial Interface Timing Diagram
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