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參數(shù)資料
| 型號： | MAX518 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs(單通道,串行,電壓輸出,8位D/A轉(zhuǎn)換器) |
| 中文描述： | 2線接口、串行、8位DAC，滿擺幅輸出 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | MAX518 |
mA
M
2-Wire S erial 8-Bit DACs with
Rail-to-Rail Outputs
4
_______________________________________________________________________________________
Note 1:
For the MAX518 (full-scale = V
DD
) the last three codes are excluded from the TUE and DNL specifications, due to the limited
output swing when loaded with 10k
to GND.
Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.
VREF_= 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
VREF_= 4Vp-p, 10kHz, DAC code = 00 hex.
Guaranteed by design.
I
C compatible mode.
Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 10:
Cb = total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V
DD
and 0.7V
DD
.
Note 11:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Hold Time, (Repeated) Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
t
HD, STA
t
LOW
t
HIGH
t
SU, STA
t
HD, DAT
t
SU, DAT
t
R
t
F
0.6
1.3
0.6
0.6
0
100
μs
μs
μs
μs
μs
ns
ns
ns
PARAMETER
SYMBOL
f
SCL
MIN
0
TYP
MAX
400
UNITS
kHz
Serial Clock Frequency
Bus Free Time Between a STOP and a
START Condition
t
BUF
1.3
μs
CONDITIONS
0.9
(Note 9)
Fall Time of SDA Transmitting (Note 7)
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
F
20 + 0.1Cb
0.6
250
ns
μs
pF
ns
t
SU, STO
Cb
t
SP
400
50
I
SINK
≤
6mA (Note 10)
20 + 0.1Cb
20 + 0.1Cb
300
300
(Note 10)
(Note 10)
0
(Notes 6, 11)
TIMING CHARACTERISTICS
(V
DD
= 5V ±10%, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)
(V
= 5V ±10%, V
REF_
= 4V (MAX517, MAX519), R
L
= 10k
, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are T
A
= +25°C.)
PARAMETER
SYMBOL
Digital-Analog Glitch Impulse
Code 128 to 127
Signal to Noise + Distortion
Ratio (MAX517, MAX519)
Code = FF hex
Multiplying Bandwidth
(MAX517, MAX519)
MIN
TYP
12
MAX UNITS
CONDITIONS
nV-s
SINAD
87
V
REF_
= 4Vp-p at 1kHz, V
DD
= 5V,
dB
1
MHz
Wideband Amplifier Noise
POWER REQUIREMENTS
60
μV
RMS
Supply Voltage
V
DD
4.5
5.5
3.0
3.5
V
1.5
1.5
MAX517E/M
MAX518C, MAX519C
MAX518E/M, MAX519E/M
MAX517C
2.5
2.5
4
5
6
V
REF_
= 4Vp-p, 3dB bandwidth
Supply Current
Normal mode, output(s)
unloaded, all digital inputs
at 0V or V
DD
I
DD
Power-down mode
20
μA
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