參數(shù)資料
型號： MAX3670EGJ
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： XO, clock
英文描述： Low-Jitter 155MHz/622MHz Clock Generator
中文描述： 670 MHz, OTHER CLOCK GENERATOR, QCC32
封裝： 5 X 5 MM, QFN-32
文件頁數(shù)： 9/13頁
文件大小： 339K
代理商： MAX3670EGJ
peaking in the PLL passband region to less than 0.1dB.
This can be achieved by setting f
Z
≤
K/100.
The three-level GSEL pins (see
Functional Diagram
)
select the phase-detector gain (K
PD
) and the frequency-
divider ratio (N
2
). Table 3 summarizes the settings for
the GSEL pins. A more detailed analysis of the loop filter
is located in application note HFDN-13.0 on
www.maxim-ic.com.
Setting the Higher-Order Poles
Spurious noise is generated by the phase detector
switching at the compare frequency, where f
COMPARE
= f
VCO
/(N
1
N
2
). Reduce the spurious noise from the
digital phase detector by placing a higher-order pole
(HOP) at a frequency much less than the compare fre-
quency. The HOP should, however, be placed high
enough in frequency that it does not decrease the over-
all loop-phase margin and impact jitter peaking. These
two conditions can be met by selecting the HOP fre-
quency to be (K
4) < f
HOP
≤
f
COMPARE
, where K is
the loop bandwidth.
The HOP can be implemented either by providing a
compensation capacitor C
2
, which produces a pole at
or by adding a lowpass filter, consisting of R
3
and C
3
,
directly on the VCO tuning port, which produces a pole at
Using R
3
and C
3
may be preferable for filtering more
noise in the PLL, but it may still be necessary to provide
filtering via C
2
when using large values of R
1
and N
1
N
2
to prevent clipping in the op amp.
Setting the Optional Output
The MAX3670 optional clock output can be set to bina-
ry subdivisions of the main clock frequency. The PSEL1
and PSEL2 pins control the binary divisions. Table 4
shows the pin configuration along with the possible
divider ratios.
Applications Information
PECL Interfacing
The MAX3670 outputs (MOUT+, MOUT-, POUT+,
POUT-) are designed to interface with PECL signal lev-
els. It is important to bias these ports appropriately. A
circuit that provides a Th
é
venin equivalent of 50
to
V
CC
- 2V can be used with fixed-impedance transmis-
sion lines with proper termination. To ensure best per-
formance, the differential outputs must have balanced
loads. It is important to note that if optional clock output
is not used, it should be left floating to save power (see
Figure 2).
f
R C
π
HOP
=
1
2
f
k
C
HOP
=
1
2(
2
)(
)
M
Low-Jitter 155MHz/622MHz
Clock Generator
_______________________________________________________________________________________
9
INPUT
PIN
GSEL1
V
CC
OPEN
GND
V
CC
OPEN
GND
V
CC
OPEN
GND
V
CC
OPEN
V
CC
OPEN
GND
V
CC
OPEN
GND
V
CC
OPEN
GND
V
CC
OPEN
INPUT
PIN
GSEL2
V
CC
V
CC
V
CC
OPEN
OPEN
OPEN
GND
GND
GND
V
CC
V
CC
V
CC
V
CC
V
CC
OPEN
OPEN
OPEN
GND
GND
GND
OPEN
OPEN
INPUT
PIN
GSEL3
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND
GND
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
GND
GND
KPD
(μA/UI)
DIVIDER
RATIO
N
2
1
2
4
8
16
32
64
128
256
512
1024
1
2
4
8
16
32
64
128
256
512
1024
20
20
20
20
20
20
20
20
20
20
20
5
5
5
5
5
5
5
5
5
5
5
Table 3. Gain Logic Pin Setup
INPUT PIN
PSEL1
V
CC
GND
V
CC
GND
INPUT PIN
PSEL2
V
CC
V
CC
GND
GND
VCO TO POUT
DIVIDER RATIO
1
2
4
8
Table 4. Setting the Optional Clock
Output Driver
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX3670EGJ-T 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low-Jitter 155MHz/622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX3670ETJ+ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low-Jitter 155MHz/622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX3670ETJ+T 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low-Jitter 155MHz/622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX3670ETJ+TD 制造商:Maxim Integrated Products 功能描述:CLOCK GEN 32QFN - Tape and Reel
MAX3670EVKIT 制造商:Microsemi Corporation 功能描述:EV Kit Is A Fully Assembled And Tested Surface-Mount Printed Circuit Board 制造商:Microsemi Corporation 功能描述:MAX3670 EVALUATION KIT - Bulk 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3670 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3670
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