參數(shù)資料
型號: MAX3109ETJ+
廠商: Maxim Integrated Products
文件頁數(shù): 33/66頁
文件大?。?/td> 0K
描述: SEMICONDUCTOR OTHER
標(biāo)準(zhǔn)包裝: 60
系列: *
Dual Serial UART with 128-Word FIFOs
MAX3109
39
Maxim Integrated
MODE2 Register
Bit 7: EchoSuprs
Set the EchoSuprs bit high to discard any data that the MAX3109 receives when its transmitter is busy transmit-
ting. In half-duplex communication such as RS-485 and IrDA, this allows blocking of the locally echoed data. The
receiver can block data for an extended time after the transmitter ceases transmission by programming a hold time in
HDplxDelay[3:0].
Bit 6: MultiDrop
Set the MultiDrop bit high to enable the 9-bit multidrop mode. If this bit is set, parity checking is not performed by the
receiver and parity generation is not done by the transmitter. The address/data indication takes the place of the parity
bit in received and transmitted data words. The parity error interrupt in LSR[2] has a different meaning in multidrop
mode: it represents the 9th bit (address/data indication) that is received with each 9-bit data character.
Bit 5: Loopback
Set the Loopback bit high to enable internal local loopback mode. This internally connects TX_ to RX_ and also RTS_
to CTS_. In local loopback mode, the TX_ output and the RX_ input are disconnected from the internal transmitter and
receiver. The TX_ output is in three-state. The RTS_ output remains connected to the internal logic and reflects the logic
state programmed in LCR[7]. The CTS_ input is disconnected from RTS_ and the internal logic. CTS_ thus remains in
a high-impedance state.
Bit 4: SpecialChr
Set the SpecialChr bit high to enable special character detection. The receiver can detect up to four special characters,
as selected in FlowCtrl[5:4] and defined in the XON1, XON2, XOFF1, and/or XOFF2 registers, optionally in combina-
tion with GPIO_ inputs if enabled through FlowCtrl[2]: GPIAddr. When a special character is received, it is put into the
RxFIFO and a special character detect interrupt is generated in ISR[1].
Special character detection can be used in addition to auto XON/XOFF flow control if enabled by FlowCtrl[3]:
SwFlowEn. In this case, XON/XOFF flow control is limited to single byte XON and XOFF characters (XON1 and XOFF1),
and only two special characters can be defined (XON2 and XOFF2).
Bit 3: RFifoEmtyInv
Set the RFifoEmtyInv bit high to invert the meaning of the receiver empty interrupt in ISR[6]: RxEmptyInt. If RFifoEmtyInv
is set low, RxEmptyInt is generated when the receive FIFO is empty. If RFifoEmtyInv is set high, RxEmptyInt is gener-
ated when data is put into the empty receive FIFO.
Bit 2: RxTrigInv
Set the RxTrigInv bit high to invert the meaning of the RxFIFO triggering. If the RxTrgInv bit is set low, an interrupt
is generated in ISR[3]: RxTrigInt when the RxFIFO fill level is filled up to above the trigger level programmed into
FIFOTrgLvl[7:4]. If RxTrigInv is set high, an interrupt is generated in ISR[3] when the RxFIFO is emptied to below the
trigger level programmed into FIFOTrgLvl[7:4].
Bit 1: FIFORst
Set the FIFORst bit high to clear all data contents from both the receive and transmit FIFOs. After a FIFO reset, set
FIFORst low to continue normal operation.
Bit 0: RST
Set the RST bit high to initiate software reset for the selected UART in the MAX3109. The I2C/SPI bus stays active dur-
ing this reset; communication with the MAX3109 is possible while RST is set. All register bits in the selected UART are
reset to their reset state and all FIFOs are cleared during a reset.
Set RST low to continue normal operation after a software reset. The MAX3109 requires reprogramming following a
software reset.
ADDRESS:
0x0A
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
EchoSuprs
MultiDrop
Loopback
SpecialChr
RFifoEmptyInv
RxTrigInv
FIFORst
RST
RESET
0
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